KMAC/UNMASKED Simulation Results

Wednesday May 21 2025 17:01:47 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	4.000s	635.687us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.730s	34.140us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.850s	21.988us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.480s	2.518ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.500s	1.941ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.570s	267.378us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.850s	21.988us	1	1	100.00
		kmac_csr_aliasing	7.500s	1.941ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.520s	14.100us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.780s	54.732us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	25.139m	188.135ms	1	1	100.00
V2	burst_write	kmac_burst_write	33.840s	5.256ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	27.925m	372.886ms	1	1	100.00
		kmac_test_vectors_sha3_256	23.170s	1.170ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.899m	359.610ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.150m	176.849ms	1	1	100.00
		kmac_test_vectors_shake_128	1.884m	7.526ms	1	1	100.00
		kmac_test_vectors_shake_256	4.330m	448.446ms	1	1	100.00
		kmac_test_vectors_kmac	2.320s	32.518us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.190s	51.877us	1	1	100.00
V2	sideload	kmac_sideload	29.480s	2.028ms	1	1	100.00
V2	app	kmac_app	37.710s	3.038ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.559m	16.261ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	20.880s	2.815ms	1	1	100.00
V2	error	kmac_error	2.703m	30.029ms	1	1	100.00
V2	key_error	kmac_key_error	4.550s	1.016ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.870s	57.800us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	21.100s	1.641ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	13.150s	909.446us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	25.990s	8.278ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	3.840s	296.462us	1	1	100.00
V2	stress_all	kmac_stress_all	2.752m	10.814ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.460s	20.718us	1	1	100.00
V2	alert_test	kmac_alert_test	1.710s	15.838us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.080s	195.854us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.080s	195.854us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.730s	34.140us	1	1	100.00
		kmac_csr_rw	1.850s	21.988us	1	1	100.00
		kmac_csr_aliasing	7.500s	1.941ms	1	1	100.00
		kmac_same_csr_outstanding	1.970s	26.285us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.730s	34.140us	1	1	100.00
		kmac_csr_rw	1.850s	21.988us	1	1	100.00
		kmac_csr_aliasing	7.500s	1.941ms	1	1	100.00
		kmac_same_csr_outstanding	1.970s	26.285us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.530s	87.740us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.530s	87.740us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.530s	87.740us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.530s	87.740us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.910s	196.654us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	35.430s	6.197ms	1	1	100.00
		kmac_tl_intg_err	3.800s	112.575us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.800s	112.575us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	3.840s	296.462us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	4.000s	635.687us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	29.480s	2.028ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.530s	87.740us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	35.430s	6.197ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	35.430s	6.197ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	35.430s	6.197ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	4.000s	635.687us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	3.840s	296.462us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	35.430s	6.197ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.224m	21.302ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	4.000s	635.687us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	52.920s	5.796ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.12445612419240899180942223071899597435861865671705586353603711377333006502465
      Line 106, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5795943920 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5795943920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---