d7d3545| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 44.000s | 3.677ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 4.000s | 13.502us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 3.000s | 26.674us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 79.364us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 4.000s | 40.824us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 8.826us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 3.000s | 26.674us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 4.000s | 40.824us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 15.000s | 1.419ms | 0 | 1 | 0.00 |
| mbx_stress_zero_delays | 1.333m | 3.558ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 19.000s | 437.975us | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 3.000s | 62.572us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 4.000s | 1.063us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 4.000s | 1.063us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 4.000s | 13.502us | 1 | 1 | 100.00 |
| mbx_csr_rw | 3.000s | 26.674us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 40.824us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 115.671us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 4.000s | 13.502us | 1 | 1 | 100.00 |
| mbx_csr_rw | 3.000s | 26.674us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 40.824us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 115.671us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 4 | 6 | 66.67 | |||
| V2S | tl_intg_err | mbx_sec_cm | 3.000s | 83.756us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 4.000s | 11.118us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 10 | 14 | 71.43 |
xmsim: *E,ASRTST (/nightly/runs/scratch/master/mbx-sim-xcelium/default/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,286): Assertion ReadyAssertedWhenRead_A has failed has 1 failures:
0.mbx_stress.42577716087569654101148089341244632019527374322033428017707123324970212780097
Line 160, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/mbx-sim-xcelium/default/src/lowrisc_ip_mbx_0.1/rtl/mbx_ombx.sv,286): (time 1418629895 PS) Assertion tb.dut.u_ombx.ReadyAssertedWhenRead_A has failed
UVM_ERROR @ 1418629895 ps: (mbx_ombx.sv:286) [ASSERT FAILED] ReadyAssertedWhenRead_A
UVM_INFO @ 1418629895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_errors.8630440089408814958565091792178852260902827744016964380258596297923420204161
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 1062931 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xcbb87a80 a_data = 0x8dd77aa8 a_mask = 0xf a_size = 0x3 a_param = 0x0 a_source = 0xfd a_opcode = Get a_user = 0x24e73 d_data = 0x357ad2fe d_size = 0x0 d_param = 0x0 d_source = 0x8a d_opcode = AccessAck d_error = 0 d_user = 1000011101111 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 1062931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_intg_err.24863434505928129092356799103908351865061752156637554850429676543830611531258
Line 99, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 11118441 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x1dc8f598 a_data = 0xdcd807c4 a_mask = 0x8 a_size = 0x2 a_param = 0x0 a_source = 0xb0 a_opcode = Get a_user = 0x201af d_data = 0xc206ab79 d_size = 0x0 d_param = 0x0 d_source = 0xb1 d_opcode = AccessAckData d_error = 0 d_user = 100010000010 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 11118441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutFullData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_csr_mem_rw_with_rand_reset.76572802933126934690503859670597754345506984908638333849191119520523072008594
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 8826240 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xefd1ec90 a_data = 0xeae0f3b5 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0xd5 a_opcode = PutFullData a_user = 0x1a8b3 d_data = 0x382544e0 d_size = 0x0 d_param = 0x0 d_source = 0x7f d_opcode = AccessAckData d_error = 0 d_user = 10110000111010 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 8826240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---