OTBN Simulation Results

Wednesday May 21 2025 17:01:47 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	135.668us	1	1	100.00
V1	single_binary	otbn_single	16.000s	43.356us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	8.000s	20.371us	1	1	100.00
V1	csr_rw	otbn_csr_rw	7.000s	16.524us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	239.918us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	37.174us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	9.000s	42.580us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	16.524us	1	1	100.00
		otbn_csr_aliasing	6.000s	37.174us	1	1	100.00
V1	mem_walk	otbn_mem_walk	21.000s	916.034us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	9.000s	70.683us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	22.000s	278.503us	1	1	100.00
V2	multi_error	otbn_multi_err	44.000s	628.040us	1	1	100.00
V2	back_to_back	otbn_multi	29.000s	74.080us	1	1	100.00
V2	stress_all	otbn_stress_all	36.000s	292.557us	1	1	100.00
V2	lc_escalation	otbn_escalate	8.000s	21.410us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	59.531us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	9.000s	69.142us	1	1	100.00
V2	alert_test	otbn_alert_test	7.000s	30.089us	1	1	100.00
V2	intr_test	otbn_intr_test	6.000s	16.598us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	7.000s	52.476us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	7.000s	52.476us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	8.000s	20.371us	1	1	100.00
		otbn_csr_rw	7.000s	16.524us	1	1	100.00
		otbn_csr_aliasing	6.000s	37.174us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	21.303us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	8.000s	20.371us	1	1	100.00
		otbn_csr_rw	7.000s	16.524us	1	1	100.00
		otbn_csr_aliasing	6.000s	37.174us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	21.303us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	10.000s	73.777us	1	1	100.00
		otbn_dmem_err	11.000s	66.521us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	9.000s	217.394us	1	1	100.00
		otbn_controller_ispr_rdata_err	11.000s	108.222us	1	1	100.00
		otbn_mac_bignum_acc_err	9.000s	53.986us	1	1	100.00
		otbn_urnd_err	7.000s	26.420us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	33.611us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	12.502us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	7.000s	15.018us	0	1	0.00
V2S	tl_intg_err	otbn_sec_cm	1.900m	2.774ms	1	1	100.00
		otbn_tl_intg_err	13.000s	123.608us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	15.000s	163.926us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	1.900m	2.774ms	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	1.900m	2.774ms	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	135.668us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	11.000s	66.521us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	73.777us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	13.000s	123.608us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	8.000s	21.410us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	73.777us	1	1	100.00
		otbn_dmem_err	11.000s	66.521us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	59.531us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	33.611us	1	1	100.00
		otbn_sec_cm	1.900m	2.774ms	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	1.900m	2.774ms	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	16.000s	43.356us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	73.777us	1	1	100.00
		otbn_dmem_err	11.000s	66.521us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	59.531us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	33.611us	1	1	100.00
		otbn_sec_cm	1.900m	2.774ms	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	1.900m	2.774ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	8.000s	21.410us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	73.777us	1	1	100.00
		otbn_dmem_err	11.000s	66.521us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	59.531us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	33.611us	1	1	100.00
		otbn_sec_cm	1.900m	2.774ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	1.900m	2.774ms	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	16.000s	43.356us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	20.727us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	55.615us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	37.000s	107.450us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	37.000s	107.450us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	33.516us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	1.900m	2.774ms	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	1.900m	2.774ms	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	10.000s	123.057us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	1.900m	2.774ms	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	1.900m	2.774ms	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	36.683us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	36.683us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	7.000s	11.837us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	16.000s	43.356us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	16.000s	43.356us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	16.000s	43.356us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	29.000s	74.080us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	16.000s	43.356us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	16.000s	43.356us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	8.000s	21.423us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	16.000s	43.356us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	1.900m	2.774ms	1	1	100.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	59.000s	2.583ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			40	41	97.56

Failure Buckets

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed has 1 failures:
  • Test otbn_partial_wipe has 1 failures.

    • 0.otbn_partial_wipe.63452560748348917839959186127901068308420617585260619106701388429256422535638
      Line 104, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_partial_wipe/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 15018096 PS) Assertion tb.MatchingStatus_A has failed
        UVM_ERROR @  15018096 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
        UVM_INFO @  15018096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---