ROM_CTRL/32KB Simulation Results

Wednesday May 21 2025 17:01:47 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	5.050s	133.535us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	5.080s	292.613us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	3.790s	214.692us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	4.000s	209.165us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	4.380s	219.264us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	5.550s	324.909us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	3.790s	214.692us	1	1	100.00
		rom_ctrl_csr_aliasing	4.380s	219.264us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	4.160s	129.507us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.140s	1.173ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.400s	576.357us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	11.760s	2.025ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	7.780s	1.176ms	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	4.040s	401.162us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	9.590s	210.146us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	9.590s	210.146us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	5.080s	292.613us	1	1	100.00
		rom_ctrl_csr_rw	3.790s	214.692us	1	1	100.00
		rom_ctrl_csr_aliasing	4.380s	219.264us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.800s	296.694us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	5.080s	292.613us	1	1	100.00
		rom_ctrl_csr_rw	3.790s	214.692us	1	1	100.00
		rom_ctrl_csr_aliasing	4.380s	219.264us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.800s	296.694us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	13.770s	414.676us	0	1	0.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	20.280s	862.117us	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.548m	862.748us	1	1	100.00
		rom_ctrl_tl_intg_err	21.010s	189.912us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.548m	862.748us	1	1	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	1.548m	862.748us	1	1	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	13.770s	414.676us	0	1	0.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	13.770s	414.676us	0	1	0.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	13.770s	414.676us	0	1	0.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	13.770s	414.676us	0	1	0.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	13.770s	414.676us	0	1	0.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.548m	862.748us	1	1	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.548m	862.748us	1	1	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	5.050s	133.535us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	5.050s	133.535us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	5.050s	133.535us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	21.010s	189.912us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	13.770s	414.676us	0	1	0.00
		rom_ctrl_kmac_err_chk	7.780s	1.176ms	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	13.770s	414.676us	0	1	0.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	13.770s	414.676us	0	1	0.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	13.770s	414.676us	0	1	0.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	20.280s	862.117us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.548m	862.748us	1	1	100.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.139m	21.079ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 1 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.30544552956098641191271590766698268390819356493598654630048800478123210462328
      Line 79, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 414675665 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 414675665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---