RV_TIMER Simulation Results

Wednesday May 21 2025 17:01:47 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.620s	44.187us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.540s	13.373us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.530s	26.706us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.110s	392.524us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.710s	32.212us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.640s	30.779us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.530s	26.706us	1	1	100.00
		rv_timer_csr_aliasing	1.710s	32.212us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.710s	97.643us	1	1	100.00
V2	disabled	rv_timer_disabled	2.170s	409.178us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	4.085m	683.039ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	4.085m	683.039ms	1	1	100.00
V2	stress	rv_timer_stress_all	1.610s	21.748us	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.490s	16.874us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.460s	29.369us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.490s	173.294us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.490s	173.294us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.540s	13.373us	1	1	100.00
		rv_timer_csr_rw	1.530s	26.706us	1	1	100.00
		rv_timer_csr_aliasing	1.710s	32.212us	1	1	100.00
		rv_timer_same_csr_outstanding	1.720s	65.334us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.540s	13.373us	1	1	100.00
		rv_timer_csr_rw	1.530s	26.706us	1	1	100.00
		rv_timer_csr_aliasing	1.710s	32.212us	1	1	100.00
		rv_timer_same_csr_outstanding	1.720s	65.334us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.980s	66.661us	1	1	100.00
		rv_timer_tl_intg_err	1.540s	289.828us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.540s	289.828us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	54.360s	7.063ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.730s	23.820us	1	1	100.00
		rv_timer_max	1.490s	12.849us	1	1	100.00
		TOTAL			19	19	100.00