SPI_DEVICE/1R1W Simulation Results

Wednesday May 21 2025 17:01:47 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.764m	128.535ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.820s	16.571us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.330s	41.158us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	18.450s	3.631ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.230s	1.260ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.500s	88.819us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.330s	41.158us	1	1	100.00
		spi_device_csr_aliasing	17.230s	1.260ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.440s	13.152us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.180s	76.803us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.890s	17.090us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.650s	1.570us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.560s	3.086us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	7.880s	283.640us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	7.880s	283.640us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.020s	898.286us	1	1	100.00
		spi_device_tpm_sts_read	1.650s	27.038us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	22.580s	23.865ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	5.800s	1.188ms	1	1	100.00
		spi_device_flash_all	2.714m	233.970ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	7.430s	11.313ms	1	1	100.00
		spi_device_flash_all	2.714m	233.970ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	7.430s	11.313ms	1	1	100.00
		spi_device_flash_all	2.714m	233.970ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	2.714m	233.970ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	8.710s	582.220us	1	1	100.00
		spi_device_flash_all	2.714m	233.970ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	8.710s	582.220us	1	1	100.00
		spi_device_flash_all	2.714m	233.970ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	8.710s	582.220us	1	1	100.00
		spi_device_flash_all	2.714m	233.970ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	8.710s	582.220us	1	1	100.00
		spi_device_flash_all	2.714m	233.970ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	8.710s	582.220us	1	1	100.00
		spi_device_flash_all	2.714m	233.970ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	7.840s	464.774us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	3.010s	68.510us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.010s	68.510us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.010s	68.510us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.340s	65.516us	1	1	100.00
		spi_device_read_buffer_direct	9.260s	1.074ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.010s	68.510us	1	1	100.00
		spi_device_flash_all	2.714m	233.970ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	2.714m	233.970ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	2.714m	233.970ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	9.440s	3.667ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	9.440s	3.667ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.764m	128.535ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.932m	122.919ms	1	1	100.00
V2	stress_all	spi_device_stress_all	7.955m	891.673ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.600s	13.324us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.620s	28.761us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.950s	360.598us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.950s	360.598us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.820s	16.571us	1	1	100.00
		spi_device_csr_rw	2.330s	41.158us	1	1	100.00
		spi_device_csr_aliasing	17.230s	1.260ms	1	1	100.00
		spi_device_same_csr_outstanding	4.020s	318.331us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.820s	16.571us	1	1	100.00
		spi_device_csr_rw	2.330s	41.158us	1	1	100.00
		spi_device_csr_aliasing	17.230s	1.260ms	1	1	100.00
		spi_device_same_csr_outstanding	4.020s	318.331us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.890s	49.818us	1	1	100.00
		spi_device_tl_intg_err	16.780s	7.056ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.780s	7.056ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	9.600s	505.012us	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.74000977262958074479648033889699746435878081015602053351963850147307792401752
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    909611 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[3])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    909611 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    909611 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[899])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.92152050593790381333880609917246576976753800948074949053231317495482786340857
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    753176 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd80cff [110110000000110011111111] vs 0x0 [0])
        UVM_ERROR @    836176 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xaca611 [101011001010011000010001] vs 0x0 [0])
        UVM_ERROR @    875176 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x607393 [11000000111001110010011] vs 0x0 [0])
        UVM_ERROR @    943176 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x358031 [1101011000000000110001] vs 0x0 [0])
        UVM_ERROR @    957176 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1bbc32 [110111011110000110010] vs 0x0 [0])