SPI_HOST Simulation Results

Wednesday May 21 2025 17:01:47 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	6.000s	134.607us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	27.705us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	18.647us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	64.361us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	64.128us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	69.710us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	18.647us	1	1	100.00
		spi_host_csr_aliasing	4.000s	64.128us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	31.472us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	38.398us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	5.000s	62.308us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	148.162us	1	1	100.00
		spi_host_error_cmd	4.000s	76.944us	1	1	100.00
		spi_host_event	40.000s	1.262ms	1	1	100.00
V2	clock_rate	spi_host_speed	5.000s	99.750us	1	1	100.00
V2	speed	spi_host_speed	5.000s	99.750us	1	1	100.00
V2	chip_select_timing	spi_host_speed	5.000s	99.750us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	5.000s	92.043us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	136.579us	1	1	100.00
V2	cpol_cpha	spi_host_speed	5.000s	99.750us	1	1	100.00
V2	full_cycle	spi_host_speed	5.000s	99.750us	1	1	100.00
V2	duplex	spi_host_smoke	6.000s	134.607us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	6.000s	134.607us	1	1	100.00
V2	stress_all	spi_host_stress_all	28.000s	3.211ms	1	1	100.00
V2	spien	spi_host_spien	16.000s	1.743ms	1	1	100.00
V2	stall	spi_host_status_stall	48.000s	2.600ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	4.000s	135.435us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	148.162us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	28.647us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	18.132us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	65.819us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	65.819us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	27.705us	1	1	100.00
		spi_host_csr_rw	3.000s	18.647us	1	1	100.00
		spi_host_csr_aliasing	4.000s	64.128us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	28.584us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	27.705us	1	1	100.00
		spi_host_csr_rw	3.000s	18.647us	1	1	100.00
		spi_host_csr_aliasing	4.000s	64.128us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	28.584us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	187.996us	1	1	100.00
		spi_host_sec_cm	4.000s	90.073us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	187.996us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	7.567m	26.786ms	1	1	100.00
		TOTAL			26	26	100.00