SRAM_CTRL/MAIN Simulation Results

Wednesday May 21 2025 17:01:47 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	12.080s	1.044ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.680s	76.162us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.600s	117.753us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.980s	165.609us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.580s	40.644us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.570s	2.539ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.600s	117.753us	1	1	100.00
		sram_ctrl_csr_aliasing	1.580s	40.644us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.802m	10.964ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	44.290s	6.394ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	5.187m	4.429ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.978m	4.258ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	16.727m	111.102ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.525m	15.379ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	36.100s	10.414ms	1	1	100.00
V2	executable	sram_ctrl_executable	8.357m	42.510ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	8.100s	1.855ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.971m	254.719ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	14.470s	3.218ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	10.170s	2.798ms	1	1	100.00
		sram_ctrl_throughput_w_readback	1.002m	3.383ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.228m	11.957ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.020s	1.404ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	27.370m	162.642ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.600s	39.662us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.950s	594.905us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.950s	594.905us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.680s	76.162us	1	1	100.00
		sram_ctrl_csr_rw	1.600s	117.753us	1	1	100.00
		sram_ctrl_csr_aliasing	1.580s	40.644us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.680s	19.479us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.680s	76.162us	1	1	100.00
		sram_ctrl_csr_rw	1.600s	117.753us	1	1	100.00
		sram_ctrl_csr_aliasing	1.580s	40.644us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.680s	19.479us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	16.350s	3.880ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.930s	14.241us	0	1	0.00
		sram_ctrl_tl_intg_err	2.140s	379.363us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.930s	14.241us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.140s	379.363us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.228m	11.957ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.228m	11.957ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.600s	117.753us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	8.357m	42.510ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	8.357m	42.510ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	8.357m	42.510ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	36.100s	10.414ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	6.600s	13.359ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	16.350s	3.880ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	7.120s	6.661ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	12.080s	1.044ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	12.080s	1.044ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	8.357m	42.510ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.930s	14.241us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	36.100s	10.414ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.930s	14.241us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.930s	14.241us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	12.080s	1.044ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.930s	14.241us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	41.760s	8.637ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.63394972204219117176365903500106512394469772005230231594776807618874135757372
      Line 101, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  14240505 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  14240505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---