SRAM_CTRL/RET Simulation Results

Wednesday May 21 2025 17:01:47 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	12.490s	459.841us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.610s	18.642us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.590s	32.765us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.330s	162.961us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.530s	40.139us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.850s	130.853us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.590s	32.765us	1	1	100.00
		sram_ctrl_csr_aliasing	1.530s	40.139us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.130s	1.336ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.150s	54.817us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	10.486m	50.478ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.704m	28.706ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	57.310s	13.514ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	9.274m	6.395ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.610s	1.465ms	1	1	100.00
V2	executable	sram_ctrl_executable	12.308m	59.060ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	1.770s	29.582us	1	1	100.00
		sram_ctrl_partial_access_b2b	5.666m	16.920ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	11.610s	309.541us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	4.170s	112.962us	1	1	100.00
		sram_ctrl_throughput_w_readback	4.490s	273.765us	1	1	100.00
V2	regwen	sram_ctrl_regwen	8.065m	8.988ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.750s	184.411us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	31.486m	183.688ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.640s	27.930us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.500s	102.169us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.500s	102.169us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.610s	18.642us	1	1	100.00
		sram_ctrl_csr_rw	1.590s	32.765us	1	1	100.00
		sram_ctrl_csr_aliasing	1.530s	40.139us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.770s	70.666us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.610s	18.642us	1	1	100.00
		sram_ctrl_csr_rw	1.590s	32.765us	1	1	100.00
		sram_ctrl_csr_aliasing	1.530s	40.139us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.770s	70.666us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.670s	3.332ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.630s	4.285us	0	1	0.00
		sram_ctrl_tl_intg_err	2.780s	639.439us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.630s	4.285us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.780s	639.439us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	8.065m	8.988ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	8.065m	8.988ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.590s	32.765us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	12.308m	59.060ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	12.308m	59.060ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	12.308m	59.060ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.610s	1.465ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.260s	204.423us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.670s	3.332ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.100s	232.269us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	12.490s	459.841us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	12.490s	459.841us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	12.308m	59.060ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.630s	4.285us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.610s	1.465ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.630s	4.285us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.630s	4.285us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	12.490s	459.841us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.630s	4.285us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	6.969m	2.052ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.41376709583278587358796309422196613881359566675910778929222151261267994383233
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4285073 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4285073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---