UART Simulation Results

Wednesday May 21 2025 17:01:47 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.100s	502.016us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.460s	121.171us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.480s	11.423us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.480s	143.706us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.480s	14.847us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.980s	37.896us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.480s	11.423us	1	1	100.00
		uart_csr_aliasing	1.480s	14.847us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	11.090s	21.257ms	1	1	100.00
V2	parity	uart_smoke	2.100s	502.016us	1	1	100.00
		uart_tx_rx	11.090s	21.257ms	1	1	100.00
V2	parity_error	uart_intr	4.440s	5.054ms	1	1	100.00
		uart_rx_parity_err	26.960s	47.180ms	1	1	100.00
V2	watermark	uart_tx_rx	11.090s	21.257ms	1	1	100.00
		uart_intr	4.440s	5.054ms	1	1	100.00
V2	fifo_full	uart_fifo_full	3.143m	169.022ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	21.410s	116.935ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	54.860s	208.796ms	1	1	100.00
V2	rx_frame_err	uart_intr	4.440s	5.054ms	1	1	100.00
V2	rx_break_err	uart_intr	4.440s	5.054ms	1	1	100.00
V2	rx_timeout	uart_intr	4.440s	5.054ms	1	1	100.00
V2	perf	uart_perf	1.785m	5.371ms	1	1	100.00
V2	sys_loopback	uart_loopback	7.900s	5.429ms	1	1	100.00
V2	line_loopback	uart_loopback	7.900s	5.429ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.273m	70.621ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	4.080s	2.297ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.990s	1.179ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	17.300s	3.359ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.710m	95.750ms	1	1	100.00
V2	stress_all	uart_stress_all	38.950s	17.191ms	1	1	100.00
V2	alert_test	uart_alert_test	1.500s	15.285us	1	1	100.00
V2	intr_test	uart_intr_test	1.480s	45.343us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.270s	137.458us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.270s	137.458us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.460s	121.171us	1	1	100.00
		uart_csr_rw	1.480s	11.423us	1	1	100.00
		uart_csr_aliasing	1.480s	14.847us	1	1	100.00
		uart_same_csr_outstanding	1.370s	57.138us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.460s	121.171us	1	1	100.00
		uart_csr_rw	1.480s	11.423us	1	1	100.00
		uart_csr_aliasing	1.480s	14.847us	1	1	100.00
		uart_same_csr_outstanding	1.370s	57.138us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.820s	124.791us	1	1	100.00
		uart_tl_intg_err	2.020s	1.145ms	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.020s	1.145ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	44.280s	17.770ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00