CHIP Simulation Results

Wednesday May 21 2025 17:01:47 UTC

GitHub Revision: `d7d3545`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.084m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.084m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.373m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.606m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.267m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.089m	5.431ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.089m	5.431ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.089m	5.431ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	38.920s	10.180us	0	1	0.00
		chip_sw_example_manufacturer	2.965m		0	1	0.00
		chip_sw_example_concurrency	4.081m	4.754ms	1	1	100.00
		chip_sw_uart_smoketest_signed	27.835s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	9.770s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	11.070s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	11.070s		0	1	0.00
V1	xbar_smoke	xbar_smoke	10.370s	11.769us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.934m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	10.346m	8.733ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.484m	3.718ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	1.169m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	48.588s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.478m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.231m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.340s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.340s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.497m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.630m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.497m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.497m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.802m	4.080ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.562m	4.705ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.939m	14.662ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.157s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.876s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	10.875m	13.732ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.573m	6.133ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	20.496m	18.021ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	20.496m	18.021ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.644s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.707m	6.084ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.707m	6.084ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	8.061m	18.016ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.551m	4.901ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.560m	5.246ms	1	1	100.00
		chip_sw_aes_idle	4.497m	4.789ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.176m	5.542ms	1	1	100.00
		chip_sw_kmac_idle	4.003m	3.763ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.677m	12.023ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	13.519m	11.645ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	11.055m	12.021ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	12.011m	12.018ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	11.966s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.713s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.878s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.934s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.158s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.628s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.817s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.966s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.713s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.878s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.934s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.158s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.628s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.817s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.774s		0	1	0.00
		chip_sw_aes_enc_jitter_en	48.660s	10.280us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	49.020s	10.240us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	48.200s	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	47.410s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.523s		0	1	0.00
		chip_sw_clkmgr_jitter	4.393m	6.081ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.542m	4.401ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	12.107s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	47.010s	10.240us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	47.320s	10.320us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	53.290s	10.320us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	51.810s	10.300us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	46.100s	10.300us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	11.117s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	12.192s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.961s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.956s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	20.217m	13.260ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.136m	15.717ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.707m	6.084ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	14.434s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.136m	15.717ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	42.712s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.011m		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	11.261s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	15.889s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.449s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	20.217m	13.260ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.939m	14.662ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	19.754m	20.019ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.120m	9.809ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	9.206m	8.340ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.702m	4.873ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	20.217m	13.260ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	12.633s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	14.312s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	20.217m	13.260ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	15.627s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	9.206m	8.340ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	12.873s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	13.667s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.602s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	12.831s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	10.788s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	12.284s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	14.312s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	15.577s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	16.741s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	15.577s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	15.577s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	15.577s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	7.115m	8.057ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	18.944s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	19.044s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	22.533s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	19.326s		0	1	0.00
		chip_sw_lc_ctrl_transition	15.577s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.644m	8.809ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	9.340m	14.941ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	12.551s		0	1	0.00
		chip_prim_tl_access	4.495m	6.285ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.966s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.713s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.878s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.934s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.158s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.628s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.817s		0	1	0.00
		chip_rv_dm_lc_disabled	10.875m	13.732ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.048m	5.732ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	48.660s	10.280us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.294m	4.048ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.497m	4.789ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.027m	5.310ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	49.020s	10.240us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.176m	5.542ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.399m	4.804ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.274m	5.230ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	47.410s	10.200us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.644m	8.809ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	15.577s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	45.540s	10.360us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.979m	5.398ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.003m	3.763ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.299s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.299s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.870s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.618m	3.278ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	11.769s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.644m	8.809ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	48.200s	10.200us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	18.525s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	12.774s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.560m	5.246ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.560m	5.246ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.560m	5.246ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.358m	5.761ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.340m	14.941ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.340m	14.941ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	7.532m	8.874ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.523s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	12.551s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	20.217m	13.260ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.497m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	15.577s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.358m	5.761ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.644m	8.809ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.532m	8.874ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.146m	3.496ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.358m	5.761ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.644m	8.809ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.532m	8.874ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.146m	3.496ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	15.577s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	13.683s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	16.741s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	18.944s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	19.044s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	22.533s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	19.326s		0	1	0.00
		chip_sw_lc_ctrl_transition	15.577s		0	1	0.00
		chip_prim_tl_access	4.495m	6.285ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.495m	6.285ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	11.242s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	16.960s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	12.192s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.774s		0	1	0.00
		chip_sw_aes_enc_jitter_en	48.660s	10.280us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	49.020s	10.240us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	48.200s	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	47.410s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.523s		0	1	0.00
		chip_sw_clkmgr_jitter	4.393m	6.081ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	9.091m	9.793ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	9.091m	9.793ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	5.188m	5.748ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.072m	5.379ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.225m	4.491ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.875m	4.448ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.888m	3.449ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	5.009m	5.607ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.146m	3.496ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	19.754m	20.019ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	19.754m	20.019ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.836m	3.574ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.419m	4.990ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.294m	3.857ms	1	1	100.00
		chip_sw_csrng_smoketest	3.074m	4.331ms	1	1	100.00
		chip_sw_gpio_smoketest	4.357m	5.149ms	1	1	100.00
		chip_sw_hmac_smoketest	4.506m	5.446ms	1	1	100.00
		chip_sw_kmac_smoketest	3.835m	5.245ms	1	1	100.00
		chip_sw_otbn_smoketest	4.902m	4.890ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.124m	3.996ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.131m	4.245ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.970m	5.288ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.059m	3.997ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.761m	5.313ms	1	1	100.00
		chip_sw_uart_smoketest	4.051m	5.737ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	38.623s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	27.835s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.934m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.159s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.548m	3.453ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.699m	4.641ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.459m	4.555ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.220m	6.168ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	19.977s		0	1	0.00
		chip_rv_dm_lc_disabled	10.875m	13.732ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	27.367s		0	1	0.00
		chip_sw_lc_walkthrough_prod	13.668s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	46.787s		0	1	0.00
		chip_sw_lc_walkthrough_rma	15.438s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	19.977s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	11.653s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	23.101s		0	1	0.00
		rom_volatile_raw_unlock	11.301s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	15.113s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.796m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.817m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.779m	3.270ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.779m	3.270ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	11.070s		0	1	0.00
		chip_same_csr_outstanding	9.720s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	11.070s		0	1	0.00
		chip_same_csr_outstanding	9.720s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	15.740s	35.308us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.590s	11.716us	1	1	100.00
		xbar_smoke_large_delays	4.494m	2.353ms	1	1	100.00
		xbar_smoke_slow_rsp	4.988m	1.958ms	1	1	100.00
		xbar_random_zero_delays	25.340s	28.056us	1	1	100.00
		xbar_random_large_delays	2.803m	1.464ms	1	1	100.00
		xbar_random_slow_rsp	25.160m	9.461ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	58.400s	116.735us	1	1	100.00
		xbar_error_and_unmapped_addr	15.100s	9.927us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.058m	172.629us	1	1	100.00
		xbar_error_and_unmapped_addr	15.100s	9.927us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	13.900s	10.041us	1	1	100.00
		xbar_access_same_device_slow_rsp	16.986m	6.245ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	2.248m	423.873us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	5.713m	252.156us	1	1	100.00
		xbar_stress_all_with_error	1.300m	83.625us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	11.884m	561.922us	1	1	100.00
		xbar_stress_all_with_reset_error	9.856m	460.369us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	11.371s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.413s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.470s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.442s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	11.440s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.880s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.367s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.059s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	10.622s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.330s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.799s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.936s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.887s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	10.876s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	12.365s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	11.882s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.456s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	11.557s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	11.641s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	11.521s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.021s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.149s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	13.239s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	12.174s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	13.062s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	13.289s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	11.510s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.003s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.102s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	11.783s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	13.131s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.617s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	11.872s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.351s		0	1	0.00
		rom_e2e_asm_init_dev	11.619s		0	1	0.00
		rom_e2e_asm_init_prod	11.615s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.963s		0	1	0.00
		rom_e2e_asm_init_rma	11.580s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.629s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.001s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.419s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.802s		0	1	0.00
V2		TOTAL			66	205	32.20
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.106m	5.038ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.929m	3.806ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	10.641s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.697s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.896s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.796s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	20.217m	13.260ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	11.444s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	16.970m	13.042ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	10.982s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	14.463s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	10.641s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.697s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.896s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.763s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.655s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.484s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.115m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	19.602m	12.823ms	1	1	100.00
		chip_plic_all_irqs_0	8.849m	7.442ms	1	1	100.00
		chip_plic_all_irqs_10	9.895m	6.332ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.634m	5.173ms	1	1	100.00
		chip_sw_dma_abort	3.994m	5.560ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.326s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.464s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.203s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.858s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.658s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.225s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.018s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.003s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.515s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.890s		0	1	0.00
		chip_sw_mbx_smoketest	4.470m	4.452ms	1	1	100.00
		TOTAL			77	247	31.17

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.79446664986505355779797387487278995089700906040483685858802161935414614291068
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (294407)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 157.888s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.115326709398021249674407138442424304400201685459684642270524739146798804132010
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (432d0b)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 139.214s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.94466947603990237742138611085703303017657378665908182116175670792873507763734
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (c492a9)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 139.219s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.14725694384272561190718652940948613983231395538257523025294839011538178368065
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (f1e98c)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 147.509s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.39825521596300602338574467376910580977504381233145222809339924128862700176457
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (4471a0)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 113.795s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.1139521047267475414135128718365984637747353706563032777682820480737772158735
    Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.10774371413550045221545328262183611763700575649551468265822530086293100457684
    Line 408, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.101658543201097441634322687564846875290807967582308320773297038941037516207243
    Line 412, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.73623334571672761831402960971737969605637127361938319769247941196965291147248
    Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.65597930605466961016659313138191482129173570255478840200703461951537392868789
    Line 410, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.23280040268313042526759307827736131439891691830063814143241770970856327997676
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.27091154055503022917081151881019547141232061948267827098415422525826059127470
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.105513024006125632079847262753196022770580299620034094815376176276293356748066
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.106987705964855731184733432705314618945034577876106351555507023170306098620488
Line 537, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20018.890752 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20018.890752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.44679472605602708370724389282827212784993965324165628590800388976628287838086
Line 454, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18020.552233 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18020.552233 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.19008996713018830236028267845469354927350193115905911273577678286483026469616
Line 482, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18015.521904 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18015.521904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.29056351088143847071098608313697725187997370923919610322973965028078545393979
Line 435, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12023.135658 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12023.135658 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.35091134699066848993255779376613290558906928443284853807359902801920312188218
Line 436, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12021.114321 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12021.114321 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.99794608680513159502923090024093455083993885840567249786252955490597446595562
Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12017.871907 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12017.871907 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.87538930462550776286904793417881905077330096616217690696800563480309891478344
Line 465, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 8809.024152 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (23368540617802589435455364897966046456707639249530731915997104601912552931754 [0x33aa2011ebe24fb803c8d30dc8a564eefbdbb65cc8cda94bd787a76989df41aa] vs 70672117159046095500322774802247952057250238880019718843958142036895730084207 [0x9c3f00347bfee7ddc959374a72189376b1bf58c30fdad91797e024552215a96f])
  UVM_INFO @ 8809.024152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.114785310860348199240655547539467538717027199534033015187704522920312484400068
Line 463, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 8057.382042 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (60673897149083862288076781399670564243019063800399740731941728115022718487274 [0x86243574ea635c7e89dd433dab2637e6161d9832a818e4557348aa235e36caea] vs 82658764178901679515457664006108500989345602709490068001071765401702364719409 [0xb6bf33dd018b52333a563e76fc4677d7a21afc78111c92718d61d66e6349a931])
  UVM_INFO @ 8057.382042 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.79939471261827018610526720274797595069041726979022389090074984479242310993381
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4079.875424 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h4a27aebd  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h36  a_opcode: 'h1  a_user: 'h248b4  d_param: 'h0  d_source: 'h36  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4079.875424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.70211208261428461393707008755413863049197028777156385002214657552936820739952
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4705.276532 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hcf00fe0e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h39  a_opcode: 'h0  a_user: 'h26962  d_param: 'h0  d_source: 'h39  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4705.276532 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.60006910914321329716784168214442995980213528442847625799528889462561584646198
    Line 398, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.56849396424721380411004101735635145321124808305868964017481696915027737609029
    Line 472, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3717.646904 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3717.646904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.114275326718972285175378708374897562775340520066408130662980987893988193524715
    Line 702, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 8339.591540 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 8339.591540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.894331634943401634288648451276421275263327499633268832629960684679029092444
    Line 470, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5748.127140 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5748.127140 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.100795150081140854202802332141208301398739569118516511553594088906655751085253
    Line 486, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 5379.272746 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 5379.272746 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.15195795437570596158177369222975112438369206571238315421586771716175595379646
    Line 435, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 6084.069712 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 6084.069712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.101651625008798880292043146055999145806269129042854774201657687399513116323373
    Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 4448.288460 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 4448.288460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.61269244256889199798099235180872186132172129857608162055605148321851738174151
    Line 434, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35880) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.109249100854771877931297909771947605125511479224523071879732404496059046123320
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3269.570284 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35880) { a_addr: 'h40590  a_data: 'he84c407e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h26  a_opcode: 'h4  a_user: 'h1a19a  d_param: 'h0  d_source: 'h26  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3269.570284 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.104100875416137495406544262454892459557910101658523883465917891637161174208058
    Line 402, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14662.115864 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14662.115864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.29413838853865261522260173466562337960127667851452848442925252768303915152015
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.102828617200414162782850884531707280038609371606120216457481464156168207715663
    Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5560.136890 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5560.136890 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```