DMA Simulation Results

Thursday May 22 2025 17:02:03 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	809.021us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	10.000s	3.092ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	362.568us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	5.000s	14.378us	1	1	100.00
V1	csr_rw	dma_csr_rw	5.000s	21.615us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	9.000s	681.743us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	6.000s	263.868us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	82.319us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	5.000s	21.615us	1	1	100.00
		dma_csr_aliasing	6.000s	263.868us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	42.000s	12.204ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	8.533m	53.810ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	3.200m	30.913ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	2.483m	23.313ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	8.533m	53.810ms	1	1	100.00
V2	dma_abort	dma_abort	7.000s	658.146us	1	1	100.00
V2	dma_stress_all	dma_stress_all	3.150m	13.762ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	14.176us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	77.426us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	77.426us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	5.000s	14.378us	1	1	100.00
		dma_csr_rw	5.000s	21.615us	1	1	100.00
		dma_csr_aliasing	6.000s	263.868us	1	1	100.00
		dma_same_csr_outstanding	5.000s	370.433us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	5.000s	14.378us	1	1	100.00
		dma_csr_rw	5.000s	21.615us	1	1	100.00
		dma_csr_aliasing	6.000s	263.868us	1	1	100.00
		dma_same_csr_outstanding	5.000s	370.433us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	22.000s	73.035us	1	1	100.00
		dma_generic_stress	2.483m	23.313ms	1	1	100.00
		dma_handshake_stress	8.533m	53.810ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	7.000s	97.330us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	2.333m	7.700ms	1	1	100.00
		dma_longer_transfer	6.000s	577.271us	1	1	100.00
		TOTAL			21	21	100.00