EDN Simulation Results

Thursday May 22 2025 17:02:03 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.930s	14.622us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.710s	29.612us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.620s	27.543us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.260s	580.819us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	2.060s	22.490us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.770s	61.604us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.620s	27.543us	1	1	100.00
		edn_csr_aliasing	2.060s	22.490us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.940s	34.101us	1	1	100.00
V2	csrng_commands	edn_genbits	1.940s	34.101us	1	1	100.00
V2	genbits	edn_genbits	1.940s	34.101us	1	1	100.00
V2	interrupts	edn_intr	1.880s	25.401us	1	1	100.00
V2	alerts	edn_alert	1.950s	113.160us	1	1	100.00
V2	errs	edn_err	1.710s	38.731us	1	1	100.00
V2	disable	edn_disable	1.610s	35.600us	1	1	100.00
		edn_disable_auto_req_mode	1.750s	41.388us	1	1	100.00
V2	stress_all	edn_stress_all	3.690s	174.882us	1	1	100.00
V2	intr_test	edn_intr_test	1.680s	136.799us	1	1	100.00
V2	alert_test	edn_alert_test	1.670s	40.663us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.630s	115.595us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.630s	115.595us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.710s	29.612us	1	1	100.00
		edn_csr_rw	1.620s	27.543us	1	1	100.00
		edn_csr_aliasing	2.060s	22.490us	1	1	100.00
		edn_same_csr_outstanding	2.000s	59.086us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.710s	29.612us	1	1	100.00
		edn_csr_rw	1.620s	27.543us	1	1	100.00
		edn_csr_aliasing	2.060s	22.490us	1	1	100.00
		edn_same_csr_outstanding	2.000s	59.086us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	4.680s	278.981us	1	1	100.00
		edn_tl_intg_err	5.970s	406.283us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.690s	27.064us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.950s	113.160us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.680s	278.981us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.680s	278.981us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.680s	278.981us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.680s	278.981us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.950s	113.160us	1	1	100.00
		edn_sec_cm	4.680s	278.981us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.950s	113.160us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	5.970s	406.283us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	55.610s	3.368ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00