HMAC Simulation Results

Thursday May 22 2025 17:02:03 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 2.120s 64.864us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.730s 116.209us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.540s 26.376us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 11.650s 2.100ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.530s 211.556us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.990s 19.391us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.540s 26.376us 1 1 100.00
hmac_csr_aliasing 4.530s 211.556us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 33.100s 2.593ms 1 1 100.00
V2 back_pressure hmac_back_pressure 13.480s 570.771us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 13.730s 189.052us 1 1 100.00
hmac_test_sha384_vectors 22.260s 256.452us 1 1 100.00
hmac_test_sha512_vectors 5.615m 76.188ms 1 1 100.00
hmac_test_hmac256_vectors 10.050s 545.264us 1 1 100.00
hmac_test_hmac384_vectors 9.170s 331.462us 1 1 100.00
hmac_test_hmac512_vectors 15.490s 399.585us 1 1 100.00
V2 burst_wr hmac_burst_wr 16.230s 1.563ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 8.745m 7.450ms 1 1 100.00
V2 error hmac_error 1.850s 17.264us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.408m 9.706ms 1 1 100.00
V2 save_and_restore hmac_smoke 2.120s 64.864us 1 1 100.00
hmac_long_msg 33.100s 2.593ms 1 1 100.00
hmac_back_pressure 13.480s 570.771us 1 1 100.00
hmac_datapath_stress 8.745m 7.450ms 1 1 100.00
hmac_burst_wr 16.230s 1.563ms 1 1 100.00
hmac_stress_all 24.495m 104.241ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 2.120s 64.864us 1 1 100.00
hmac_long_msg 33.100s 2.593ms 1 1 100.00
hmac_back_pressure 13.480s 570.771us 1 1 100.00
hmac_datapath_stress 8.745m 7.450ms 1 1 100.00
hmac_wipe_secret 1.408m 9.706ms 1 1 100.00
hmac_test_sha256_vectors 13.730s 189.052us 1 1 100.00
hmac_test_sha384_vectors 22.260s 256.452us 1 1 100.00
hmac_test_sha512_vectors 5.615m 76.188ms 1 1 100.00
hmac_test_hmac256_vectors 10.050s 545.264us 1 1 100.00
hmac_test_hmac384_vectors 9.170s 331.462us 1 1 100.00
hmac_test_hmac512_vectors 15.490s 399.585us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 2.120s 64.864us 1 1 100.00
hmac_long_msg 33.100s 2.593ms 1 1 100.00
hmac_back_pressure 13.480s 570.771us 1 1 100.00
hmac_datapath_stress 8.745m 7.450ms 1 1 100.00
hmac_burst_wr 16.230s 1.563ms 1 1 100.00
hmac_error 1.850s 17.264us 1 1 100.00
hmac_wipe_secret 1.408m 9.706ms 1 1 100.00
hmac_test_sha256_vectors 13.730s 189.052us 1 1 100.00
hmac_test_sha384_vectors 22.260s 256.452us 1 1 100.00
hmac_test_sha512_vectors 5.615m 76.188ms 1 1 100.00
hmac_test_hmac256_vectors 10.050s 545.264us 1 1 100.00
hmac_test_hmac384_vectors 9.170s 331.462us 1 1 100.00
hmac_test_hmac512_vectors 15.490s 399.585us 1 1 100.00
hmac_stress_all 24.495m 104.241ms 1 1 100.00
V2 stress_all hmac_stress_all 24.495m 104.241ms 1 1 100.00
V2 alert_test hmac_alert_test 1.440s 51.638us 1 1 100.00
V2 intr_test hmac_intr_test 1.580s 14.493us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.900s 68.448us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.900s 68.448us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.730s 116.209us 1 1 100.00
hmac_csr_rw 1.540s 26.376us 1 1 100.00
hmac_csr_aliasing 4.530s 211.556us 1 1 100.00
hmac_same_csr_outstanding 1.890s 25.051us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.730s 116.209us 1 1 100.00
hmac_csr_rw 1.540s 26.376us 1 1 100.00
hmac_csr_aliasing 4.530s 211.556us 1 1 100.00
hmac_same_csr_outstanding 1.890s 25.051us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.870s 129.160us 1 1 100.00
hmac_tl_intg_err 3.030s 239.539us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.030s 239.539us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 2.120s 64.864us 1 1 100.00
V3 stress_reset hmac_stress_reset 2.110s 133.968us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.319m 28.064ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.910s 122.431us 1 1 100.00
TOTAL 28 28 100.00