I2C Simulation Results

Thursday May 22 2025 17:02:03 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	15.380s	3.952ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	18.310s	781.793us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.610s	26.586us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.610s	24.751us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.210s	189.098us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.160s	105.724us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.860s	26.559us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.610s	24.751us	1	1	100.00
		i2c_csr_aliasing	2.160s	105.724us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	3.380s	481.713us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	15.539m	67.831ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	10.780s	3.100ms	1	1	100.00
V2	host_override	i2c_host_override	1.610s	26.417us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.366m	9.719ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.261m	6.909ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.410s	144.461us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.660s	2.010ms	1	1	100.00
		i2c_host_fifo_reset_rx	8.380s	1.022ms	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.454m	2.282ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	7.560s	1.590ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.510s	118.714us	1	1	100.00
V2	target_glitch	i2c_target_glitch	7.390s	2.196ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	6.825m	28.832ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.860s	559.202us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	28.780s	4.053ms	1	1	100.00
		i2c_target_intr_smoke	7.420s	1.127ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.240s	411.508us	1	1	100.00
		i2c_target_fifo_reset_tx	2.200s	688.893us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	6.580s	12.451ms	1	1	100.00
		i2c_target_stress_rd	28.780s	4.053ms	1	1	100.00
		i2c_target_intr_stress_wr	5.010s	2.566ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	7.230s	2.101ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	8.590s	2.655ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	8.260s	4.869ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	10.870s	10.024ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.130s	1.016ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.850s	127.519us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	10.780s	3.100ms	1	1	100.00
		i2c_host_perf_precise	2.440m	23.196ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	7.560s	1.590ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	5.830s	541.186us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.320s	657.883us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.960s	1.909ms	1	1	100.00
		i2c_target_nack_txstretch	1.970s	722.214us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	6.100s	937.418us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.700s	855.830us	1	1	100.00
V2	alert_test	i2c_alert_test	1.520s	37.630us	1	1	100.00
V2	intr_test	i2c_intr_test	1.530s	15.309us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.810s	453.472us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.810s	453.472us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.610s	26.586us	1	1	100.00
		i2c_csr_rw	1.610s	24.751us	1	1	100.00
		i2c_csr_aliasing	2.160s	105.724us	1	1	100.00
		i2c_same_csr_outstanding	1.980s	56.563us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.610s	26.586us	1	1	100.00
		i2c_csr_rw	1.610s	24.751us	1	1	100.00
		i2c_csr_aliasing	2.160s	105.724us	1	1	100.00
		i2c_same_csr_outstanding	1.980s	56.563us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.240s	1.079ms	1	1	100.00
		i2c_sec_cm	1.990s	70.494us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.240s	1.079ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	10.470s	2.289ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.340s	683.669us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	6.580s	295.784us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.40025255362097379598393508530518239099970796021125638000367750061924875113024
      Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2289053733 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2289053733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.64660975188084844930554887325329985056966208948385060910629871063731547015418
      Line 87, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 295783654 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 295783654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.112913281523114792384585508533445251042799481802852162641290809180151155561745
      Line 238, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 67831338853 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @18138492
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.13954240127826564835464766029581034855168181997123399705717847537941532933092
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 683669139 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 175 [0xaf])
        UVM_INFO @ 683669139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.20453063824861485113319025723251693924505596440596720944467037011412151582101
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10023856287 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10023856287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.31643449519055099531293379352887112125390701970190319560097258207896833248973
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 722213780 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 722213780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---