KMAC/MASKED Simulation Results

Thursday May 22 2025 17:02:03 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	51.230s	2.743ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.920s	256.264us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.830s	65.684us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.340s	155.184us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.900s	249.060us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.050s	43.451us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.830s	65.684us	1	1	100.00
		kmac_csr_aliasing	3.900s	249.060us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.750s	36.406us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.110s	149.717us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	8.692m	118.306ms	1	1	100.00
V2	burst_write	kmac_burst_write	8.939m	7.223ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	25.050m	53.303ms	1	1	100.00
		kmac_test_vectors_sha3_256	24.095m	61.167ms	1	1	100.00
		kmac_test_vectors_sha3_384	22.230s	1.426ms	1	1	100.00
		kmac_test_vectors_sha3_512	17.210s	937.282us	1	1	100.00
		kmac_test_vectors_shake_128	2.720m	16.586ms	1	1	100.00
		kmac_test_vectors_shake_256	23.318m	18.134ms	1	1	100.00
		kmac_test_vectors_kmac	2.930s	115.559us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.960s	220.990us	1	1	100.00
V2	sideload	kmac_sideload	5.096m	109.976ms	1	1	100.00
V2	app	kmac_app	4.360m	14.793ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.532m	5.515ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.933m	8.378ms	1	1	100.00
V2	error	kmac_error	1.002m	19.448ms	1	1	100.00
V2	key_error	kmac_key_error	6.550s	949.783us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.960s	103.561us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	26.630s	509.882us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	37.190s	8.392ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	52.500s	6.535ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.060s	99.082us	1	1	100.00
V2	stress_all	kmac_stress_all	13.938m	25.704ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.580s	34.281us	1	1	100.00
V2	alert_test	kmac_alert_test	1.740s	39.347us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.530s	125.675us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.530s	125.675us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.920s	256.264us	1	1	100.00
		kmac_csr_rw	1.830s	65.684us	1	1	100.00
		kmac_csr_aliasing	3.900s	249.060us	1	1	100.00
		kmac_same_csr_outstanding	1.960s	79.579us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.920s	256.264us	1	1	100.00
		kmac_csr_rw	1.830s	65.684us	1	1	100.00
		kmac_csr_aliasing	3.900s	249.060us	1	1	100.00
		kmac_same_csr_outstanding	1.960s	79.579us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.280s	42.829us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.280s	42.829us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.280s	42.829us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.280s	42.829us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.830s	12.987us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	1.233m	7.085ms	1	1	100.00
		kmac_tl_intg_err	1.820s	109.796us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.820s	109.796us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.060s	99.082us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	51.230s	2.743ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	5.096m	109.976ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.280s	42.829us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.233m	7.085ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.233m	7.085ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.233m	7.085ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	51.230s	2.743ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.060s	99.082us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.233m	7.085ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.289m	95.905ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	51.230s	2.743ms	1	1	100.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.751m	24.828ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	40	95.00

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.18988089115700079396197177018400653509710641115151319203939142278201246421972
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
        UVM_ERROR @  12987024 ps: (kmac_csr_assert_fpv.sv:525) [ASSERT FAILED] prefix_6_rd_A
        UVM_INFO @  12987024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.64762266782110410736917657177304158680725615412138651280465853621861305631675
      Line 79, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
        UVM_ERROR @ 109796378 ps: (kmac_csr_assert_fpv.sv:505) [ASSERT FAILED] prefix_2_rd_A
        UVM_INFO @ 109796378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---