601f9c3| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 58.000s | 2.233ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 4.000s | 31.934us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 4.000s | 92.623us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 5.000s | 122.503us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 4.000s | 30.260us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 1.174us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 4.000s | 92.623us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 4.000s | 30.260us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 40.000s | 743.155us | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 34.000s | 2.772ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 35.000s | 3.228ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 5.000s | 21.784us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 5.000s | 1.755us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 5.000s | 1.755us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 4.000s | 31.934us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 92.623us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 30.260us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 13.990us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 4.000s | 31.934us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 92.623us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 30.260us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 13.990us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 5.000s | 41.112us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 4.000s | 5.964us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutFullData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_errors.18090001867824936870482946308100563296475437242879038345747696181992573674258
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 1754964 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x4507d8bc a_data = 0x1bc5909b a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0xf4 a_opcode = PutFullData a_user = 0x1ba3f d_data = 0x841149b d_size = 0x2 d_param = 0x0 d_source = 0xc1 d_opcode = AccessAck d_error = 0 d_user = 1011000100 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 1754964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutPartialData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_intg_err.22306148776152380587288518163320653826322550730198633979097013183687204645646
Line 96, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 5963514 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xcc627574 a_data = 0xa6e5539f a_mask = 0xe a_size = 0x2 a_param = 0x0 a_source = 0x91 a_opcode = PutPartialData a_user = 0x2511e d_data = 0x3cfd3eab d_size = 0x0 d_param = 0x0 d_source = 0x69 d_opcode = AccessAckData d_error = 0 d_user = 10010111001101 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 5963514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutFullData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_csr_mem_rw_with_rand_reset.56019193374048862230840515333846148584280733961858103405206358912181593139320
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 1173848 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xce327810 a_data = 0x53d74a38 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0xf7 a_opcode = PutFullData a_user = 0x18e99 d_data = 0xe483438a d_size = 0x2 d_param = 0x0 d_source = 0x6c d_opcode = AccessAckData d_error = 0 d_user = 10100101000100 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 1173848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---