ROM_CTRL/32KB Simulation Results

Thursday May 22 2025 17:02:03 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.260s 882.397us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 4.880s 889.253us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.060s 2.089ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 3.880s 959.216us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 3.870s 210.694us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.220s 137.041us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.060s 2.089ms 1 1 100.00
rom_ctrl_csr_aliasing 3.870s 210.694us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.990s 167.694us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.620s 576.858us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.370s 632.414us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 13.170s 1.628ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 8.430s 1.045ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 3.810s 1.694ms 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 6.070s 201.606us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 6.070s 201.606us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 4.880s 889.253us 1 1 100.00
rom_ctrl_csr_rw 4.060s 2.089ms 1 1 100.00
rom_ctrl_csr_aliasing 3.870s 210.694us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.120s 225.316us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 4.880s 889.253us 1 1 100.00
rom_ctrl_csr_rw 4.060s 2.089ms 1 1 100.00
rom_ctrl_csr_aliasing 3.870s 210.694us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.120s 225.316us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.072m 15.800ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 17.520s 1.181ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.171m 2.018ms 1 1 100.00
rom_ctrl_tl_intg_err 23.110s 235.983us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.171m 2.018ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 3.171m 2.018ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.072m 15.800ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.072m 15.800ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.072m 15.800ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.072m 15.800ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.072m 15.800ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.171m 2.018ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.171m 2.018ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.260s 882.397us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.260s 882.397us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.260s 882.397us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 23.110s 235.983us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.072m 15.800ms 1 1 100.00
rom_ctrl_kmac_err_chk 8.430s 1.045ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.072m 15.800ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.072m 15.800ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.072m 15.800ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 17.520s 1.181ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.171m 2.018ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 49.630s 2.040ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00