ROM_CTRL/64KB Simulation Results

Thursday May 22 2025 17:02:03 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 8.360s 2.350ms 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 11.850s 214.727us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 5.920s 757.988us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.150s 214.262us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 9.170s 547.749us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.670s 383.492us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 5.920s 757.988us 1 1 100.00
rom_ctrl_csr_aliasing 9.170s 547.749us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 10.610s 556.549us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.440s 539.646us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.450s 226.164us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 27.690s 4.245ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 15.000s 2.026ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 9.790s 2.281ms 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.860s 1.008ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.860s 1.008ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 11.850s 214.727us 1 1 100.00
rom_ctrl_csr_rw 5.920s 757.988us 1 1 100.00
rom_ctrl_csr_aliasing 9.170s 547.749us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.760s 1.065ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 11.850s 214.727us 1 1 100.00
rom_ctrl_csr_rw 5.920s 757.988us 1 1 100.00
rom_ctrl_csr_aliasing 9.170s 547.749us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.760s 1.065ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.912m 14.057ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 39.990s 1.570ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.054m 1.336ms 1 1 100.00
rom_ctrl_tl_intg_err 1.096m 996.218us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.054m 1.336ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 5.054m 1.336ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.912m 14.057ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.912m 14.057ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.912m 14.057ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.912m 14.057ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.912m 14.057ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.054m 1.336ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.054m 1.336ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 8.360s 2.350ms 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 8.360s 2.350ms 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 8.360s 2.350ms 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.096m 996.218us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.912m 14.057ms 1 1 100.00
rom_ctrl_kmac_err_chk 15.000s 2.026ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.912m 14.057ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.912m 14.057ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.912m 14.057ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 39.990s 1.570ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.054m 1.336ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.933m 15.398ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00