RV_DM/USE_DMI_INTERFACE Simulation Results

Thursday May 22 2025 17:02:03 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 5.850s 4.385ms 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.810s 630.608us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 1.850s 96.546us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 22.350s 19.217ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 3.350s 943.775us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 14.920s 6.181ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 8.610s 6.921ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 19.260s 9.255ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.032m 64.068ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.910s 202.414us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 3.020s 916.496us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 2.160s 375.240us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.900s 160.897us 0 1 0.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.700s 108.822us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.940s 943.068us 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.990s 228.387us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.300s 217.487us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 1.910s 202.414us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 2.140s 573.638us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.820s 294.653us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 2.160s 375.240us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.800s 145.122us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.480s 485.764us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.710s 144.350us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 29.540s 3.735ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 19.000s 824.382us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 2.600s 53.282us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 19.000s 824.382us 1 1 100.00
rv_dm_csr_rw 2.710s 144.350us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.790s 57.009us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.740s 33.808us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 5.850s 4.385ms 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.940s 794.363us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 2.080s 398.561us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.740s 218.690us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 1.730s 604.911us 1 1 100.00
V2 sba rv_dm_sba_tl_access 9.980s 3.954ms 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 1.620s 46.342us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 4.030s 2.069ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 10.020s 13.308ms 0 1 0.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 2.450s 516.951us 0 1 0.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 5.070s 1.961ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 2.250s 354.965us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 1.440s 259.355us 0 1 0.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 11.220s 9.383ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 1.810s 88.114us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.750s 112.710us 1 1 100.00
V2 stress_all rv_dm_stress_all 0 1 0.00
V2 alert_test rv_dm_alert_test 1.720s 113.925us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.600s 38.641us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.600s 38.641us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 19.000s 824.382us 1 1 100.00
rv_dm_csr_hw_reset 2.480s 485.764us 1 1 100.00
rv_dm_csr_rw 2.710s 144.350us 1 1 100.00
rv_dm_same_csr_outstanding 6.720s 261.222us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 19.000s 824.382us 1 1 100.00
rv_dm_csr_hw_reset 2.480s 485.764us 1 1 100.00
rv_dm_csr_rw 2.710s 144.350us 1 1 100.00
rv_dm_same_csr_outstanding 6.720s 261.222us 1 1 100.00
V2 TOTAL 11 19 57.89
V2S tl_intg_err rv_dm_sec_cm 3.100s 629.778us 1 1 100.00
rv_dm_tl_intg_err 6.480s 901.304us 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 6.480s 901.304us 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 5.070s 1.961ms 1 1 100.00
rv_dm_debug_disabled 1.800s 54.542us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 5.070s 1.961ms 1 1 100.00
rv_dm_debug_disabled 1.800s 54.542us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 5.850s 4.385ms 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 1.900s 406.495us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.750s 101.209us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.750s 101.209us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 1.900s 406.495us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.900s 59.441us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 2.441m 300.000ms 0 1 0.00
TOTAL 42 53 79.25

Failure Buckets