RV_TIMER Simulation Results

Thursday May 22 2025 17:02:03 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.570s	39.521us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.500s	37.758us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.720s	12.620us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.970s	4.629ms	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.750s	62.887us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.820s	66.046us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.720s	12.620us	1	1	100.00
		rv_timer_csr_aliasing	1.750s	62.887us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.800s	294.546us	1	1	100.00
V2	disabled	rv_timer_disabled	2.570s	1.711ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	1.670s	500.563us	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	1.670s	500.563us	1	1	100.00
V2	stress	rv_timer_stress_all	1.540s	199.939us	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.450s	33.508us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.550s	47.592us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.460s	813.996us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.460s	813.996us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.500s	37.758us	1	1	100.00
		rv_timer_csr_rw	1.720s	12.620us	1	1	100.00
		rv_timer_csr_aliasing	1.750s	62.887us	1	1	100.00
		rv_timer_same_csr_outstanding	1.620s	28.499us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.500s	37.758us	1	1	100.00
		rv_timer_csr_rw	1.720s	12.620us	1	1	100.00
		rv_timer_csr_aliasing	1.750s	62.887us	1	1	100.00
		rv_timer_same_csr_outstanding	1.620s	28.499us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.790s	239.395us	1	1	100.00
		rv_timer_tl_intg_err	2.380s	194.476us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.380s	194.476us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	4.940s	5.643ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.390s	26.998us	1	1	100.00
		rv_timer_max	1.480s	25.785us	1	1	100.00
		TOTAL			19	19	100.00