SPI_DEVICE/1R1W Simulation Results

Thursday May 22 2025 17:02:03 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	49.840s	2.992ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.920s	16.833us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.150s	46.138us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	8.450s	1.003ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.310s	332.849us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.330s	44.242us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.150s	46.138us	1	1	100.00
		spi_device_csr_aliasing	6.310s	332.849us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.640s	9.949us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.420s	207.641us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.680s	112.738us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.590s	2.803us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.670s	3.946us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	6.320s	198.160us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	6.320s	198.160us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	7.920s	8.924ms	1	1	100.00
		spi_device_tpm_sts_read	2.110s	162.002us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	18.470s	3.519ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.850s	127.253us	1	1	100.00
		spi_device_flash_all	6.590s	1.774ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	5.340s	487.908us	1	1	100.00
		spi_device_flash_all	6.590s	1.774ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	5.340s	487.908us	1	1	100.00
		spi_device_flash_all	6.590s	1.774ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	6.590s	1.774ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	8.720s	2.406ms	1	1	100.00
		spi_device_flash_all	6.590s	1.774ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	8.720s	2.406ms	1	1	100.00
		spi_device_flash_all	6.590s	1.774ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	8.720s	2.406ms	1	1	100.00
		spi_device_flash_all	6.590s	1.774ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	8.720s	2.406ms	1	1	100.00
		spi_device_flash_all	6.590s	1.774ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	8.720s	2.406ms	1	1	100.00
		spi_device_flash_all	6.590s	1.774ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.640s	645.751us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	3.750s	244.898us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.750s	244.898us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.750s	244.898us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.780s	218.400us	1	1	100.00
		spi_device_read_buffer_direct	4.500s	460.212us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.750s	244.898us	1	1	100.00
		spi_device_flash_all	6.590s	1.774ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	6.590s	1.774ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	6.590s	1.774ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	8.310s	2.529ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	8.310s	2.529ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	49.840s	2.992ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	3.887m	160.909ms	1	1	100.00
V2	stress_all	spi_device_stress_all	4.962m	210.192ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.680s	70.067us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.660s	14.787us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.320s	134.002us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.320s	134.002us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.920s	16.833us	1	1	100.00
		spi_device_csr_rw	2.150s	46.138us	1	1	100.00
		spi_device_csr_aliasing	6.310s	332.849us	1	1	100.00
		spi_device_same_csr_outstanding	3.490s	122.883us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.920s	16.833us	1	1	100.00
		spi_device_csr_rw	2.150s	46.138us	1	1	100.00
		spi_device_csr_aliasing	6.310s	332.849us	1	1	100.00
		spi_device_same_csr_outstanding	3.490s	122.883us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.030s	746.142us	1	1	100.00
		spi_device_tl_intg_err	13.320s	1.247ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	13.320s	1.247ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	43.000s	18.183ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.114623516710071766936849754690085623260916375245958177319580482348687879297383
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2136038 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[69])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2136038 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2136038 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[965])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.42277627226839080001770454592009890381417362944679966976374029137368100893001
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1155753 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd630c [11010110001100001100] vs 0x0 [0])
        UVM_ERROR @   1246753 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x875d04 [100001110101110100000100] vs 0x0 [0])
        UVM_ERROR @   1314753 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9acab0 [100110101100101010110000] vs 0x0 [0])
        UVM_ERROR @   1397753 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7f6052 [11111110110000001010010] vs 0x0 [0])
        UVM_ERROR @   1471753 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbeb3c4 [101111101011001111000100] vs 0x0 [0])