SPI_HOST Simulation Results

Thursday May 22 2025 17:02:03 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	19.000s	2.940ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	165.096us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	171.885us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	131.204us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	65.543us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	63.271us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	171.885us	1	1	100.00
		spi_host_csr_aliasing	4.000s	65.543us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	19.503us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	26.906us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	5.000s	23.973us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	81.921us	1	1	100.00
		spi_host_error_cmd	4.000s	20.401us	1	1	100.00
		spi_host_event	14.000s	846.102us	1	1	100.00
V2	clock_rate	spi_host_speed	6.000s	398.044us	1	1	100.00
V2	speed	spi_host_speed	6.000s	398.044us	1	1	100.00
V2	chip_select_timing	spi_host_speed	6.000s	398.044us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	10.000s	833.938us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	60.254us	1	1	100.00
V2	cpol_cpha	spi_host_speed	6.000s	398.044us	1	1	100.00
V2	full_cycle	spi_host_speed	6.000s	398.044us	1	1	100.00
V2	duplex	spi_host_smoke	19.000s	2.940ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	19.000s	2.940ms	1	1	100.00
V2	stress_all	spi_host_stress_all	7.000s	352.875us	1	1	100.00
V2	spien	spi_host_spien	1.550m	25.743ms	1	1	100.00
V2	stall	spi_host_status_stall	45.000s	1.417ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	7.000s	117.230us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	81.921us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	17.630us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	50.909us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	220.947us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	220.947us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	165.096us	1	1	100.00
		spi_host_csr_rw	4.000s	171.885us	1	1	100.00
		spi_host_csr_aliasing	4.000s	65.543us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	22.027us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	165.096us	1	1	100.00
		spi_host_csr_rw	4.000s	171.885us	1	1	100.00
		spi_host_csr_aliasing	4.000s	65.543us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	22.027us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	82.369us	1	1	100.00
		spi_host_sec_cm	4.000s	291.467us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	82.369us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	10.617m	54.307ms	1	1	100.00
		TOTAL			26	26	100.00