SRAM_CTRL/MAIN Simulation Results

Thursday May 22 2025 17:02:03 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	9.080s	8.535ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.700s	17.126us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.460s	182.644us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.440s	122.241us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.590s	16.702us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.200s	3.080ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.460s	182.644us	1	1	100.00
		sram_ctrl_csr_aliasing	1.590s	16.702us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.120m	82.784ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	53.780s	4.356ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.563m	70.222ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.147m	7.588ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	17.649m	545.022ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.401m	11.816ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.135m	18.318ms	1	1	100.00
V2	executable	sram_ctrl_executable	4.752m	22.572ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	37.980s	4.908ms	1	1	100.00
		sram_ctrl_partial_access_b2b	2.958m	8.714ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	26.090s	737.884us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	44.680s	817.583us	1	1	100.00
		sram_ctrl_throughput_w_readback	1.103m	928.983us	1	1	100.00
V2	regwen	sram_ctrl_regwen	12.299m	30.739ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.770s	724.597us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	46.252m	142.729ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.650s	18.111us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.860s	33.020us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.860s	33.020us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.700s	17.126us	1	1	100.00
		sram_ctrl_csr_rw	1.460s	182.644us	1	1	100.00
		sram_ctrl_csr_aliasing	1.590s	16.702us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.700s	15.357us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.700s	17.126us	1	1	100.00
		sram_ctrl_csr_rw	1.460s	182.644us	1	1	100.00
		sram_ctrl_csr_aliasing	1.590s	16.702us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.700s	15.357us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	42.550s	28.235ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.720s	22.332us	0	1	0.00
		sram_ctrl_tl_intg_err	3.040s	752.018us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.720s	22.332us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.040s	752.018us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	12.299m	30.739ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	12.299m	30.739ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.460s	182.644us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.752m	22.572ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.752m	22.572ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.752m	22.572ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.135m	18.318ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.470s	2.657ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	42.550s	28.235ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.270s	1.429ms	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	9.080s	8.535ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	9.080s	8.535ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.752m	22.572ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.720s	22.332us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.135m	18.318ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.720s	22.332us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.720s	22.332us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	9.080s	8.535ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.720s	22.332us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	12.690s	325.335us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.66102506103496021090578769430419787756470969926762353005089547938179161739282
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 1429478086 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x66) != exp (0x13)
        UVM_INFO @ 1429478086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.94577913513194736680718894566485400944867313956813298711425845790296385867506
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  22331570 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  22331570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---