SRAM_CTRL/RET Simulation Results

Thursday May 22 2025 17:02:03 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	9.010s	176.164us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.700s	48.019us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.690s	24.434us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.930s	28.391us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.690s	222.461us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.760s	54.781us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.690s	24.434us	1	1	100.00
		sram_ctrl_csr_aliasing	1.690s	222.461us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.730s	705.222us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.730s	1.220ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	7.745m	9.848ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.468m	2.795ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	14.560s	453.518us	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	2.055m	1.107ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	6.810s	2.862ms	1	1	100.00
V2	executable	sram_ctrl_executable	43.440s	20.868ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	11.820s	753.368us	1	1	100.00
		sram_ctrl_partial_access_b2b	5.776m	161.356ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	3.130s	161.585us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	6.970s	279.091us	1	1	100.00
		sram_ctrl_throughput_w_readback	10.380s	279.195us	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.972m	2.425ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.670s	66.441us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	13.103m	13.238ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.550s	26.538us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.110s	237.030us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.110s	237.030us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.700s	48.019us	1	1	100.00
		sram_ctrl_csr_rw	1.690s	24.434us	1	1	100.00
		sram_ctrl_csr_aliasing	1.690s	222.461us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.610s	16.373us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.700s	48.019us	1	1	100.00
		sram_ctrl_csr_rw	1.690s	24.434us	1	1	100.00
		sram_ctrl_csr_aliasing	1.690s	222.461us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.610s	16.373us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.630s	1.296ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.630s	9.432us	0	1	0.00
		sram_ctrl_tl_intg_err	4.030s	634.447us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.630s	9.432us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.030s	634.447us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.972m	2.425ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.972m	2.425ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.690s	24.434us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	43.440s	20.868ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	43.440s	20.868ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	43.440s	20.868ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	6.810s	2.862ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.680s	133.647us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.630s	1.296ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.650s	24.533us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	9.010s	176.164us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	9.010s	176.164us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	43.440s	20.868ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.630s	9.432us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	6.810s	2.862ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.630s	9.432us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.630s	9.432us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	9.010s	176.164us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.630s	9.432us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.833m	5.579ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.8444896836580757311868176171703999173853348993423043261277123873060184165046
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  24533434 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x4f) != exp (0x7b)
        UVM_INFO @  24533434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.87756871946750080782865857972016943692665556385424498149345080171440081804250
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   9432000 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   9432000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---