UART Simulation Results

Thursday May 22 2025 17:02:03 UTC

GitHub Revision: 601f9c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.750s	865.215us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.590s	66.956us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.500s	14.208us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.210s	272.604us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.540s	69.806us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.780s	29.013us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.500s	14.208us	1	1	100.00
		uart_csr_aliasing	1.540s	69.806us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	34.050s	117.980ms	1	1	100.00
V2	parity	uart_smoke	2.750s	865.215us	1	1	100.00
		uart_tx_rx	34.050s	117.980ms	1	1	100.00
V2	parity_error	uart_intr	13.220s	32.263ms	1	1	100.00
		uart_rx_parity_err	2.359m	100.178ms	1	1	100.00
V2	watermark	uart_tx_rx	34.050s	117.980ms	1	1	100.00
		uart_intr	13.220s	32.263ms	1	1	100.00
V2	fifo_full	uart_fifo_full	16.280s	34.221ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	39.880s	119.583ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	1.978m	179.147ms	1	1	100.00
V2	rx_frame_err	uart_intr	13.220s	32.263ms	1	1	100.00
V2	rx_break_err	uart_intr	13.220s	32.263ms	1	1	100.00
V2	rx_timeout	uart_intr	13.220s	32.263ms	1	1	100.00
V2	perf	uart_perf	4.505m	11.442ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.150s	3.171ms	1	1	100.00
V2	line_loopback	uart_loopback	3.150s	3.171ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.630s	340.381us	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	23.020s	44.241ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.770s	1.001ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	26.900s	6.512ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.569m	60.413ms	1	1	100.00
V2	stress_all	uart_stress_all	4.652m	162.023ms	1	1	100.00
V2	alert_test	uart_alert_test	1.560s	52.484us	1	1	100.00
V2	intr_test	uart_intr_test	1.550s	12.137us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.010s	24.790us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.010s	24.790us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.590s	66.956us	1	1	100.00
		uart_csr_rw	1.500s	14.208us	1	1	100.00
		uart_csr_aliasing	1.540s	69.806us	1	1	100.00
		uart_same_csr_outstanding	1.530s	27.226us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.590s	66.956us	1	1	100.00
		uart_csr_rw	1.500s	14.208us	1	1	100.00
		uart_csr_aliasing	1.540s	69.806us	1	1	100.00
		uart_same_csr_outstanding	1.530s	27.226us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.650s	36.054us	1	1	100.00
		uart_tl_intg_err	1.690s	142.291us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.690s	142.291us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	41.370s	4.898ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00