CHIP Simulation Results

Thursday May 22 2025 17:02:03 UTC

GitHub Revision: `601f9c3`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.203m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.203m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.737m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.653m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.623m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.868m	5.910ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.868m	5.910ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.868m	5.910ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	37.730s	10.220us	0	1	0.00
		chip_sw_example_manufacturer	2.689m		0	1	0.00
		chip_sw_example_concurrency	4.418m	4.679ms	1	1	100.00
		chip_sw_uart_smoketest_signed	22.566s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	9.660s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	9.610s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	9.610s		0	1	0.00
V1	xbar_smoke	xbar_smoke	8.870s	12.587us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	2.078m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	10.677m	10.017ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.371m	3.981ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	1.363m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	1.239m		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.540m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.530m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.790s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.790s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.132m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.145m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.143m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.143m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.078m	4.147ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.309m	4.418ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.483m	14.774ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.140s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.536s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	10.013m	16.295ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.990m	6.032ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	20.102m	18.025ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	20.102m	18.025ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.343s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.279m	5.532ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.279m	5.532ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.596m	18.021ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.765m	5.521ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.321m	5.666ms	1	1	100.00
		chip_sw_aes_idle	3.694m	5.497ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.928m	5.126ms	1	1	100.00
		chip_sw_kmac_idle	4.469m	5.502ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.738m	12.018ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	10.716m	12.025ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	12.319m	12.016ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	12.623m	11.527ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	12.067s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.022s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.311s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.312s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.409s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.721s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.430s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	12.067s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.022s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.311s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.312s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.409s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.721s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.430s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.716s		0	1	0.00
		chip_sw_aes_enc_jitter_en	1.039m	10.340us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	1.018m	10.360us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.042m	10.220us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	53.610s	10.240us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.998s		0	1	0.00
		chip_sw_clkmgr_jitter	4.303m	4.190ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.822m	4.095ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.887s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	48.180s	10.340us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	48.950s	10.360us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	46.920s	10.340us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	55.350s	10.260us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	54.070s	10.300us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	14.547s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.862s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	10.775s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.227s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	19.702m	12.973ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.722m	15.203ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	6.279m	5.532ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	10.515s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.722m	15.203ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	17.287s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	13.915s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	12.350s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	23.362s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	54.821s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	19.702m	12.973ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.483m	14.774ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	21.458m	20.022ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.787m	10.153ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	8.339m	6.567ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.753m	4.969ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	19.702m	12.973ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	11.693s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.488s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	19.702m	12.973ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	11.016s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	8.339m	6.567ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	11.744s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	12.471s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.821s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	11.230s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.836s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	11.843s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.488s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	13.807s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	15.882s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	13.807s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	13.807s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	13.807s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	7.273m	9.744ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	26.682s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	49.669s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	21.680s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	16.092s		0	1	0.00
		chip_sw_lc_ctrl_transition	13.807s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.727m	7.975ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	9.866m	14.262ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.217s		0	1	0.00
		chip_prim_tl_access	13.887m	23.420ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	12.067s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.022s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.311s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.312s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.409s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.721s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.430s		0	1	0.00
		chip_rv_dm_lc_disabled	10.013m	16.295ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.889m	5.108ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.039m	10.340us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.731m	3.914ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.694m	5.497ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.406m	4.856ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.018m	10.360us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.928m	5.126ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.364m	3.868ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.719m	3.987ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	53.610s	10.240us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.727m	7.975ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	13.807s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	40.230s	10.380us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.626m	3.812ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.469m	5.502ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.821s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.821s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.881s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.982m	5.051ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	11.928s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.727m	7.975ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.042m	10.220us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	10.614s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	10.716s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.321m	5.666ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.321m	5.666ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.321m	5.666ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.172m	4.724ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.866m	14.262ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.866m	14.262ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	7.938m	7.733ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.998s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.217s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	19.702m	12.973ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.143m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	13.807s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.172m	4.724ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.727m	7.975ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.938m	7.733ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.010m	4.330ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.172m	4.724ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.727m	7.975ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.938m	7.733ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.010m	4.330ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	13.807s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	10.830s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	15.882s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	26.682s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	49.669s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	21.680s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	16.092s		0	1	0.00
		chip_sw_lc_ctrl_transition	13.807s		0	1	0.00
		chip_prim_tl_access	13.887m	23.420ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	13.887m	23.420ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	28.414s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	15.376s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.862s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.716s		0	1	0.00
		chip_sw_aes_enc_jitter_en	1.039m	10.340us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	1.018m	10.360us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.042m	10.220us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	53.610s	10.240us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.998s		0	1	0.00
		chip_sw_clkmgr_jitter	4.303m	4.190ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	8.480m	10.449ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	8.480m	10.449ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.593m	3.757ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.712m	4.411ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.744m	4.416ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.458m	5.838ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.780m	3.750ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.207m	5.870ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.010m	4.330ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	21.458m	20.022ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	21.458m	20.022ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.426m	3.640ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.341m	4.131ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.085m	3.995ms	1	1	100.00
		chip_sw_csrng_smoketest	2.983m	3.967ms	1	1	100.00
		chip_sw_gpio_smoketest	3.227m	3.615ms	1	1	100.00
		chip_sw_hmac_smoketest	4.011m	5.645ms	1	1	100.00
		chip_sw_kmac_smoketest	3.576m	5.714ms	1	1	100.00
		chip_sw_otbn_smoketest	4.111m	3.783ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.151m	5.732ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.096m	5.611ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.565m	5.440ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.475m	4.420ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.183m	5.092ms	1	1	100.00
		chip_sw_uart_smoketest	3.212m	5.296ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	22.974s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	22.566s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.078m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.093s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.229m	4.286ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.262m	5.770ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.220m	5.633ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.904m	6.051ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	39.009s		0	1	0.00
		chip_rv_dm_lc_disabled	10.013m	16.295ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	37.023s		0	1	0.00
		chip_sw_lc_walkthrough_prod	14.882s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	12.342s		0	1	0.00
		chip_sw_lc_walkthrough_rma	13.150s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	39.009s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	12.047s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	16.350s		0	1	0.00
		rom_volatile_raw_unlock	12.634s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.911s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.965m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.095m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.462m	5.116ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.462m	5.116ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	9.610s		0	1	0.00
		chip_same_csr_outstanding	13.020s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	9.610s		0	1	0.00
		chip_same_csr_outstanding	13.020s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	1.970m	323.094us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.190s	12.215us	1	1	100.00
		xbar_smoke_large_delays	4.032m	2.142ms	1	1	100.00
		xbar_smoke_slow_rsp	5.513m	2.168ms	1	1	100.00
		xbar_random_zero_delays	20.250s	21.062us	1	1	100.00
		xbar_random_large_delays	17.199m	8.824ms	1	1	100.00
		xbar_random_slow_rsp	29.767m	11.463ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	49.020s	76.357us	1	1	100.00
		xbar_error_and_unmapped_addr	33.400s	72.692us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	2.382m	472.971us	1	1	100.00
		xbar_error_and_unmapped_addr	33.400s	72.692us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	3.386m	632.743us	1	1	100.00
		xbar_access_same_device_slow_rsp	32.916m	12.848ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	47.250s	42.604us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	3.135m	419.659us	1	1	100.00
		xbar_stress_all_with_error	18.478m	3.468ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	10.351m	539.690us	1	1	100.00
		xbar_stress_all_with_reset_error	1.160m	28.228us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	12.770s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	13.705s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	13.890s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.485s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.778s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	12.072s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.356s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.149s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.710s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	10.418s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.316s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.756s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.170s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.200s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.713s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.703s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.494s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.341s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	12.398s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.142s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.706s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	11.727s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.442s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	12.316s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.290s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.847s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.535s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	13.164s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	11.768s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	11.680s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	11.909s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.836s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.754s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.269s		0	1	0.00
		rom_e2e_asm_init_dev	10.896s		0	1	0.00
		rom_e2e_asm_init_prod	11.209s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.718s		0	1	0.00
		rom_e2e_asm_init_rma	11.491s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.009s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.987s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.820s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	10.848s		0	1	0.00
V2		TOTAL			66	205	32.20
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.649m	4.562ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.236m	5.282ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.819s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.761s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.531s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.367s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	19.702m	12.973ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	19.695s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	16.201m	14.265ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	10.959s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	11.910s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.819s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.761s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.531s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.632s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.121s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.627s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	56.529s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	20.106m	12.212ms	1	1	100.00
		chip_plic_all_irqs_0	8.057m	7.053ms	1	1	100.00
		chip_plic_all_irqs_10	8.811m	6.058ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.420m	5.305ms	1	1	100.00
		chip_sw_dma_abort	4.324m	5.226ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.611s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.686s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.738s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	12.035s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.687s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.790s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.696s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.461s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	12.184s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.761s		0	1	0.00
		chip_sw_mbx_smoketest	3.828m	5.800ms	1	1	100.00
		TOTAL			77	247	31.17

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.108699015165891012620123192373902212637344950868098504293788762626502830112823
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0d57ba)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 151.278s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.20009247331281017357998023459969647187861404910102380025456751078446463448587
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (449936)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 117.680s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.58836914330393358287032688559224211232017291408994485106755800443857800576249
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (46a630)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 117.070s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.115558843060404089209896176319592481565437622930052547811012915177264781530437
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (8c16ad)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 118.173s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.30469085200206654805559391808935438341167666008955890466362102613590005995116
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (c31fd1)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 121.285s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.36475454622408751321885538869965028413990759176494542110468264458829076167807
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.102232906927925076032704412665426133243997591013500653228256896766897322978297
    Line 411, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.25343620107682326471828355894396133563067333311427284532820491318323961964354
    Line 408, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.21509890883794512736296223080064173454967210387961186284046892536737063009661
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.818122634877578074120605916952890319991040514329863955153822870477710521455
    Line 423, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.81964944947773958746391316436787055708912256801917710691608063756794008688992
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.21107627030084192706032841568074493290127282378594675211804631613838462448133
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.53881642725265281922018384377752016164284781402386657154763933260721475758823
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.34348205616848142933964363142209988260198261517348856181879355910133249856730
Line 518, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20022.468838 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20022.468838 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.49341952590770671703541074682633664685486444823306378094694879435872003049886
Line 468, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18024.712625 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18024.712625 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.51365902245598915463272340829025389222985987936319391918644546130613881641599
Line 453, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18020.609867 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18020.609867 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.44422933392889981897866962697236051953660489225131147744082025556390717305043
Line 433, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12018.024158 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.024158 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.99830793313991274372968062499836508908707471001513541952554976656446259255548
Line 438, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12024.728118 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12024.728118 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.112616345382312436582265132319453666006546311669870703242207908733801247143506
Line 431, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12016.492180 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12016.492180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.79125631773701337715302921683991880905246806383328677181180931109448233089733
Line 465, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 7974.727486 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (22446299081229793245423402020951900679418161418613830356733709193229882898858 [0x31a027b21f6747299110b4c4157ad7ab46a387d27ec8b5ba360aa2ba161c39aa] vs 62869598768453692184021222453593092862566756494300728670727513758493177630199 [0x8afeee906e96be92ec14c523a03e1538d029a5bf3cbc24398d905fbee1ed4df7])
  UVM_INFO @ 7974.727486 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.8314042192147222244009149547567541351098381379186149181154911711972224041773
Line 461, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 9744.488696 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (98356877873409172697495067182777142454051598210620633253136040474633574860108 [0xd9740523b4613859562b5a00318607b14a3838420b707e5a0390e53e66e4c54c] vs 51228118711668358669423052734380727832428672012479427452411381867817105858474 [0x714216722278da603792ee4bf8b273ffd44e26d63183fd075373bcd918cb9faa])
  UVM_INFO @ 9744.488696 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.24652825603691724930072928844967717481470467307969272879315693631083427768654
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4146.926775 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hdcfb3613  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h7  a_opcode: 'h0  a_user: 'h26918  d_param: 'h0  d_source: 'h7  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4146.926775 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.62755069177559965764694813165958081602934369706714033067395792891675169484186
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4417.618272 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hbc73b1bd  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h6  a_opcode: 'h1  a_user: 'h248d8  d_param: 'h0  d_source: 'h6  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4417.618272 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.106022150469283316548441932317187051166144764026824507435429586774970759266340
    Line 609, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.89921519146970628918541323796974779727565361390391328296208406598195386663259
    Line 486, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3981.302700 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3981.302700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.104248146500541131413069452500627925374049660457967104143906144025119552674453
    Line 691, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 6566.506700 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 6566.506700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.74522455921474938088507979943147951581560106262032657570672218102539832308644
    Line 474, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 3756.898950 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3756.898950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.35251513581970285618702784155112184447349589167507863519321236026097087865825
    Line 471, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4410.613884 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4410.613884 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.115203796674010196491621389761500966463772498942181268363167574041810174291808
    Line 423, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 5532.201780 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 5532.201780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.32560080018277562216624232602639994945444052137898395229365261045117743351966
    Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5837.912988 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5837.912988 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.7358808052768306679143848234058760411525621032710894711352079647564414107081
    Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@36402) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.105042537470815977145734677690100031826570326316566068216002043710950409643966
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 5115.866664 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@36402) { a_addr: 'h1465110  a_data: 'hf17069be  a_mask: 'h5  a_size: 'h2  a_param: 'h0  a_source: 'hb8  a_opcode: 'h4  a_user: 'h2514a  d_param: 'h0  d_source: 'hb8  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5115.866664 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.100040025007082544205160587518078462393623283087811057934786974427291597101590
    Line 405, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14773.772296 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14773.772296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.109579966466071869505593608360930073849813260499194458683313576110394656817826
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.92001386877065455951971081264025781318957636595477183738754700890192341699333
    Line 420, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5225.635446 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5225.635446 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```