DMA Simulation Results

Monday May 26 2025 17:08:21 UTC

GitHub Revision: 9bdf6bb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	1.149ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	9.000s	3.414ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	8.000s	3.702ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	26.917us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	34.449us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	8.000s	160.597us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	9.000s	1.741ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	73.081us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	34.449us	1	1	100.00
		dma_csr_aliasing	9.000s	1.741ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	58.000s	4.023ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	3.433m	37.963ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	3.100m	298.663ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	3.333m	35.720ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	3.433m	37.963ms	1	1	100.00
V2	dma_abort	dma_abort	9.000s	2.042ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	2.600m	16.150ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	104.676us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	88.614us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	88.614us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	26.917us	1	1	100.00
		dma_csr_rw	4.000s	34.449us	1	1	100.00
		dma_csr_aliasing	9.000s	1.741ms	1	1	100.00
		dma_same_csr_outstanding	5.000s	86.608us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	26.917us	1	1	100.00
		dma_csr_rw	4.000s	34.449us	1	1	100.00
		dma_csr_aliasing	9.000s	1.741ms	1	1	100.00
		dma_same_csr_outstanding	5.000s	86.608us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	32.000s	499.925us	1	1	100.00
		dma_generic_stress	3.333m	35.720ms	1	1	100.00
		dma_handshake_stress	3.433m	37.963ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	6.000s	359.376us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.233m	4.049ms	1	1	100.00
		dma_longer_transfer	11.000s	2.139ms	1	1	100.00
		TOTAL			21	21	100.00