EDN Simulation Results

Monday May 26 2025 17:08:21 UTC

GitHub Revision: 9bdf6bb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.940s	17.791us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.650s	58.803us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.750s	68.510us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	2.500s	135.053us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	2.300s	67.395us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.420s	36.078us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.750s	68.510us	1	1	100.00
		edn_csr_aliasing	2.300s	67.395us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.160s	57.644us	1	1	100.00
V2	csrng_commands	edn_genbits	2.160s	57.644us	1	1	100.00
V2	genbits	edn_genbits	2.160s	57.644us	1	1	100.00
V2	interrupts	edn_intr	1.590s	32.385us	1	1	100.00
V2	alerts	edn_alert	2.260s	59.911us	1	1	100.00
V2	errs	edn_err	1.800s	23.457us	1	1	100.00
V2	disable	edn_disable	1.830s	20.582us	1	1	100.00
		edn_disable_auto_req_mode	1.850s	37.644us	1	1	100.00
V2	stress_all	edn_stress_all	2.750s	362.129us	1	1	100.00
V2	intr_test	edn_intr_test	1.730s	12.789us	1	1	100.00
V2	alert_test	edn_alert_test	1.800s	31.145us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.510s	100.173us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.510s	100.173us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.650s	58.803us	1	1	100.00
		edn_csr_rw	1.750s	68.510us	1	1	100.00
		edn_csr_aliasing	2.300s	67.395us	1	1	100.00
		edn_same_csr_outstanding	2.280s	36.016us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.650s	58.803us	1	1	100.00
		edn_csr_rw	1.750s	68.510us	1	1	100.00
		edn_csr_aliasing	2.300s	67.395us	1	1	100.00
		edn_same_csr_outstanding	2.280s	36.016us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	4.350s	240.167us	1	1	100.00
		edn_tl_intg_err	3.460s	110.592us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.610s	44.873us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	2.260s	59.911us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.350s	240.167us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.350s	240.167us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.350s	240.167us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.350s	240.167us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	2.260s	59.911us	1	1	100.00
		edn_sec_cm	4.350s	240.167us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	2.260s	59.911us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.460s	110.592us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	42.810s	2.130ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00