HMAC Simulation Results

Monday May 26 2025 17:08:21 UTC

GitHub Revision: 9bdf6bb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 10.390s 2.721ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.830s 166.615us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.670s 95.753us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 10.620s 309.895us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.060s 665.084us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.050s 21.309us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.670s 95.753us 1 1 100.00
hmac_csr_aliasing 3.060s 665.084us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 48.810s 28.555ms 1 1 100.00
V2 back_pressure hmac_back_pressure 26.880s 576.180us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 2.942m 8.024ms 1 1 100.00
hmac_test_sha384_vectors 21.150s 1.639ms 1 1 100.00
hmac_test_sha512_vectors 19.440s 220.723us 1 1 100.00
hmac_test_hmac256_vectors 9.880s 321.429us 1 1 100.00
hmac_test_hmac384_vectors 10.200s 1.349ms 1 1 100.00
hmac_test_hmac512_vectors 9.000s 823.092us 1 1 100.00
V2 burst_wr hmac_burst_wr 18.530s 18.212ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 10.657m 4.707ms 1 1 100.00
V2 error hmac_error 1.209m 75.639ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 24.030s 849.595us 1 1 100.00
V2 save_and_restore hmac_smoke 10.390s 2.721ms 1 1 100.00
hmac_long_msg 48.810s 28.555ms 1 1 100.00
hmac_back_pressure 26.880s 576.180us 1 1 100.00
hmac_datapath_stress 10.657m 4.707ms 1 1 100.00
hmac_burst_wr 18.530s 18.212ms 1 1 100.00
hmac_stress_all 17.806m 105.989ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 10.390s 2.721ms 1 1 100.00
hmac_long_msg 48.810s 28.555ms 1 1 100.00
hmac_back_pressure 26.880s 576.180us 1 1 100.00
hmac_datapath_stress 10.657m 4.707ms 1 1 100.00
hmac_wipe_secret 24.030s 849.595us 1 1 100.00
hmac_test_sha256_vectors 2.942m 8.024ms 1 1 100.00
hmac_test_sha384_vectors 21.150s 1.639ms 1 1 100.00
hmac_test_sha512_vectors 19.440s 220.723us 1 1 100.00
hmac_test_hmac256_vectors 9.880s 321.429us 1 1 100.00
hmac_test_hmac384_vectors 10.200s 1.349ms 1 1 100.00
hmac_test_hmac512_vectors 9.000s 823.092us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 10.390s 2.721ms 1 1 100.00
hmac_long_msg 48.810s 28.555ms 1 1 100.00
hmac_back_pressure 26.880s 576.180us 1 1 100.00
hmac_datapath_stress 10.657m 4.707ms 1 1 100.00
hmac_burst_wr 18.530s 18.212ms 1 1 100.00
hmac_error 1.209m 75.639ms 1 1 100.00
hmac_wipe_secret 24.030s 849.595us 1 1 100.00
hmac_test_sha256_vectors 2.942m 8.024ms 1 1 100.00
hmac_test_sha384_vectors 21.150s 1.639ms 1 1 100.00
hmac_test_sha512_vectors 19.440s 220.723us 1 1 100.00
hmac_test_hmac256_vectors 9.880s 321.429us 1 1 100.00
hmac_test_hmac384_vectors 10.200s 1.349ms 1 1 100.00
hmac_test_hmac512_vectors 9.000s 823.092us 1 1 100.00
hmac_stress_all 17.806m 105.989ms 1 1 100.00
V2 stress_all hmac_stress_all 17.806m 105.989ms 1 1 100.00
V2 alert_test hmac_alert_test 1.570s 14.288us 1 1 100.00
V2 intr_test hmac_intr_test 1.580s 18.491us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.950s 68.566us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.950s 68.566us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.830s 166.615us 1 1 100.00
hmac_csr_rw 1.670s 95.753us 1 1 100.00
hmac_csr_aliasing 3.060s 665.084us 1 1 100.00
hmac_same_csr_outstanding 2.980s 481.675us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.830s 166.615us 1 1 100.00
hmac_csr_rw 1.670s 95.753us 1 1 100.00
hmac_csr_aliasing 3.060s 665.084us 1 1 100.00
hmac_same_csr_outstanding 2.980s 481.675us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.680s 277.282us 1 1 100.00
hmac_tl_intg_err 2.390s 210.645us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.390s 210.645us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 10.390s 2.721ms 1 1 100.00
V3 stress_reset hmac_stress_reset 5.470s 111.698us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 42.960s 6.016ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.670s 422.368us 1 1 100.00
TOTAL 28 28 100.00