I2C Simulation Results

Monday May 26 2025 17:08:21 UTC

GitHub Revision: `9bdf6bb`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	47.020s	1.467ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	9.350s	1.016ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.500s	36.895us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.550s	27.619us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.690s	935.594us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.570s	199.406us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.130s	35.598us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.550s	27.619us	1	1	100.00
		i2c_csr_aliasing	2.570s	199.406us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	3.250s	101.960us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	2.965m	9.602ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	3.390s	192.486us	1	1	100.00
V2	host_override	i2c_host_override	1.550s	17.317us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.349m	10.514ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	26.040s	1.535ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.890s	174.100us	1	1	100.00
		i2c_host_fifo_fmt_empty	3.980s	1.604ms	1	1	100.00
		i2c_host_fifo_reset_rx	10.230s	483.572us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.198m	13.716ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	17.110s	557.331us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.940s	249.413us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.460s	1.942ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	21.182m	64.286ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.640s	3.938ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	6.010s	1.626ms	1	1	100.00
		i2c_target_intr_smoke	3.520s	2.732ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.060s	1.124ms	1	1	100.00
		i2c_target_fifo_reset_tx	2.070s	694.178us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	8.830s	21.926ms	1	1	100.00
		i2c_target_stress_rd	6.010s	1.626ms	1	1	100.00
		i2c_target_intr_stress_wr	26.860s	20.935ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	6.430s	8.026ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	3.650s	10.009ms	0	1	0.00
V2	bad_address	i2c_target_bad_addr	4.540s	11.749ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	3.020s	1.554ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.610s	475.796us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.040s	626.993us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	3.390s	192.486us	1	1	100.00
		i2c_host_perf_precise	3.030s	298.867us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	17.110s	557.331us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.180s	140.303us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.640s	931.662us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.820s	496.528us	1	1	100.00
		i2c_target_nack_txstretch	2.130s	1.629ms	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	10.530s	2.094ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.460s	1.535ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.660s	24.191us	1	1	100.00
V2	intr_test	i2c_intr_test	1.540s	20.802us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.170s	72.796us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.170s	72.796us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.500s	36.895us	1	1	100.00
		i2c_csr_rw	1.550s	27.619us	1	1	100.00
		i2c_csr_aliasing	2.570s	199.406us	1	1	100.00
		i2c_same_csr_outstanding	2.150s	93.237us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.500s	36.895us	1	1	100.00
		i2c_csr_rw	1.550s	27.619us	1	1	100.00
		i2c_csr_aliasing	2.570s	199.406us	1	1	100.00
		i2c_same_csr_outstanding	2.150s	93.237us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.510s	138.373us	1	1	100.00
		i2c_sec_cm	1.760s	252.118us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.510s	138.373us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	6.720s	620.935us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.270s	23.142us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	11.570s	8.487ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 2 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.64035654190494613293638968091030866975661072393254392628673364837832387239842
Line 190, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 9602320623 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4063950

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.17294760689551643054912791056292212938846853823878147245989967489340859361931
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 249412618 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @38371

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.24014441998431878733876201213715982228074456436098234653963529155127078686952
    Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 620934698 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 620934698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.24035234888698045703960377396444304184727580746473601487634881963971131517617
    Line 97, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8486781620 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8486781620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 1 failures:
- Test i2c_target_stretch has 1 failures.
  - 0.i2c_target_stretch.21895129456867854344359160624737141645226717074600323086781291282351147861814
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10008773444 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10008773444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.56275213954202752928098339085505411411372984804865844863921206447133303983710
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  23141814 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 219 [0xdb])
  UVM_INFO @  23141814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```