KEYMGR Simulation Results

Monday May 26 2025 17:08:21 UTC

GitHub Revision: `9bdf6bb`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.920s	117.468us	1	1	100.00
V1	random	keymgr_random	3.320s	266.700us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.830s	38.411us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.860s	29.409us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	3.020s	172.206us	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	11.430s	461.835us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.110s	26.676us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.860s	29.409us	1	1	100.00
		keymgr_csr_aliasing	11.430s	461.835us	0	1	0.00
V1		TOTAL			5	7	71.43
V2	cfgen_during_op	keymgr_cfg_regwen	3.480s	312.656us	1	1	100.00
V2	sideload	keymgr_sideload	14.760s	696.095us	1	1	100.00
		keymgr_sideload_kmac	2.620s	33.310us	1	1	100.00
		keymgr_sideload_aes	3.400s	367.878us	1	1	100.00
		keymgr_sideload_otbn	5.550s	1.245ms	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	3.930s	192.843us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.720s	45.349us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.370s	140.561us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	7.090s	447.346us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.660s	247.360us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.150s	81.672us	1	1	100.00
V2	stress_all	keymgr_stress_all	17.780s	2.910ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.790s	20.596us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.730s	369.709us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.900s	120.338us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.900s	120.338us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.830s	38.411us	1	1	100.00
		keymgr_csr_rw	1.860s	29.409us	1	1	100.00
		keymgr_csr_aliasing	11.430s	461.835us	0	1	0.00
		keymgr_same_csr_outstanding	3.360s	200.072us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.830s	38.411us	1	1	100.00
		keymgr_csr_rw	1.860s	29.409us	1	1	100.00
		keymgr_csr_aliasing	11.430s	461.835us	0	1	0.00
		keymgr_same_csr_outstanding	3.360s	200.072us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	5.300s	1.736ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	5.300s	1.736ms	1	1	100.00
		keymgr_tl_intg_err	5.220s	227.777us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.020s	353.854us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.020s	353.854us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.020s	353.854us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.020s	353.854us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	6.040s	3.535ms	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	5.300s	1.736ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	5.300s	1.736ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	5.220s	227.777us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.020s	353.854us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.480s	312.656us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	3.320s	266.700us	1	1	100.00
		keymgr_csr_rw	1.860s	29.409us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	3.320s	266.700us	1	1	100.00
		keymgr_csr_rw	1.860s	29.409us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	3.320s	266.700us	1	1	100.00
		keymgr_csr_rw	1.860s	29.409us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.720s	45.349us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.660s	247.360us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.660s	247.360us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	3.320s	266.700us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.660s	86.768us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	5.300s	1.736ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	5.300s	1.736ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	5.300s	1.736ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.820s	185.313us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.720s	45.349us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	5.300s	1.736ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	5.300s	1.736ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	5.300s	1.736ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.820s	185.313us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.820s	185.313us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	5.300s	1.736ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.820s	185.313us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	5.300s	1.736ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.820s	185.313us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	3.410s	462.925us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			27	30	90.00

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

Test keymgr_csr_bit_bash has 1 failures.

0.keymgr_csr_bit_bash.52644034503542979008305168764869232458724606556391703880076917961667652791671
Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
  UVM_ERROR @ 172206193 ps: (keymgr_csr_assert_fpv.sv:419) [ASSERT FAILED] sealing_sw_binding_5_rd_A
  UVM_INFO @ 172206193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_csr_aliasing has 1 failures.

0.keymgr_csr_aliasing.10737327013102878368056306356498135187252100397883380986131124767834014441792
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
  UVM_ERROR @ 461835147 ps: (keymgr_csr_assert_fpv.sv:459) [ASSERT FAILED] attest_sw_binding_5_rd_A
  UVM_INFO @ 461835147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 0.keymgr_stress_all_with_rand_reset.57312848691508934198681882504322515917875036837471477273822965013081062569955
    Line 322, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 462925375 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 462925375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```