| V1 |
smoke |
keymgr_dpe_smoke |
20.980s |
1.739ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
1.830s |
13.152us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
1.700s |
10.565us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
4.800s |
317.229us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
3.090s |
168.779us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
1.930s |
212.549us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
1.700s |
10.565us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
3.090s |
168.779us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
1.820s |
12.710us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
1.850s |
140.812us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
2.380s |
547.545us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
2.380s |
547.545us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
1.830s |
13.152us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.700s |
10.565us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
3.090s |
168.779us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.920s |
65.592us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
1.830s |
13.152us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.700s |
10.565us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
3.090s |
168.779us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.920s |
65.592us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
5.770s |
494.912us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
5.370s |
262.495us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
2.430s |
144.188us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
2.430s |
144.188us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
2.430s |
144.188us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
2.430s |
144.188us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
4.780s |
3.829ms |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
5.770s |
494.912us |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
5.770s |
494.912us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |