KMAC/MASKED Simulation Results

Monday May 26 2025 17:08:21 UTC

GitHub Revision: 9bdf6bb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	6.730s	799.985us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.850s	52.822us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.710s	161.223us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.200s	571.313us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.510s	249.319us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.110s	151.168us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.710s	161.223us	1	1	100.00
		kmac_csr_aliasing	4.510s	249.319us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.870s	12.519us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.160s	94.518us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	16.743m	50.203ms	1	1	100.00
V2	burst_write	kmac_burst_write	19.351m	164.493ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	24.147m	19.011ms	1	1	100.00
		kmac_test_vectors_sha3_256	34.950s	2.347ms	1	1	100.00
		kmac_test_vectors_sha3_384	1.830s	94.814us	0	1	0.00
		kmac_test_vectors_sha3_512	17.710s	996.360us	1	1	100.00
		kmac_test_vectors_shake_128	31.918m	69.062ms	1	1	100.00
		kmac_test_vectors_shake_256	1.867m	7.472ms	1	1	100.00
		kmac_test_vectors_kmac	3.720s	178.155us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.930s	84.656us	1	1	100.00
V2	sideload	kmac_sideload	2.897m	7.172ms	1	1	100.00
V2	app	kmac_app	1.400m	1.909ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.914m	17.001ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.381m	19.056ms	1	1	100.00
V2	error	kmac_error	1.264m	16.577ms	1	1	100.00
V2	key_error	kmac_key_error	3.180s	182.366us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	6.550s	463.784us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.590s	38.739us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.880s	47.378us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	48.280s	32.045ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	15.080s	5.466ms	1	1	100.00
V2	stress_all	kmac_stress_all	10.007m	36.463ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.620s	42.083us	1	1	100.00
V2	alert_test	kmac_alert_test	1.620s	55.616us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.820s	152.735us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.820s	152.735us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.850s	52.822us	1	1	100.00
		kmac_csr_rw	1.710s	161.223us	1	1	100.00
		kmac_csr_aliasing	4.510s	249.319us	1	1	100.00
		kmac_same_csr_outstanding	2.390s	113.589us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.850s	52.822us	1	1	100.00
		kmac_csr_rw	1.710s	161.223us	1	1	100.00
		kmac_csr_aliasing	4.510s	249.319us	1	1	100.00
		kmac_same_csr_outstanding	2.390s	113.589us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.330s	263.785us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.330s	263.785us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.330s	263.785us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.330s	263.785us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.930s	17.653us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	34.670s	15.374ms	1	1	100.00
		kmac_tl_intg_err	2.620s	213.892us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.620s	213.892us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	15.080s	5.466ms	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	6.730s	799.985us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.897m	7.172ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.330s	263.785us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	34.670s	15.374ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	34.670s	15.374ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	34.670s	15.374ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	6.730s	799.985us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	15.080s	5.466ms	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	34.670s	15.374ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.879m	72.138ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	6.730s	799.985us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	39.570s	1.994ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:

  • Test kmac_test_vectors_sha3_384 has 1 failures.

    • 0.kmac_test_vectors_sha3_384.82863726595161903592942289709011336996709286308038108438408649857715487105790
      Line 73, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_384/latest/run.log

        UVM_ERROR @  94814282 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @  94814282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.52571094006455239542143929555283449668302520452483615550850867648821957019585
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
        UVM_ERROR @  17653230 ps: (kmac_csr_assert_fpv.sv:535) [ASSERT FAILED] prefix_8_rd_A
        UVM_INFO @  17653230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---