9bdf6bb| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 34.000s | 6.759ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 4.000s | 18.625us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 3.000s | 14.833us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 40.377us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 4.000s | 12.554us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 1.017us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 3.000s | 14.833us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 4.000s | 12.554us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 28.000s | 574.744us | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 31.000s | 1.974ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 39.000s | 2.049ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 4.000s | 38.858us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 4.000s | 2.272us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 4.000s | 2.272us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 4.000s | 18.625us | 1 | 1 | 100.00 |
| mbx_csr_rw | 3.000s | 14.833us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 12.554us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 42.313us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 4.000s | 18.625us | 1 | 1 | 100.00 |
| mbx_csr_rw | 3.000s | 14.833us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 12.554us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 42.313us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 4.000s | 11.816us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 4.000s | 32.595us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutFullData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 2 failures:
Test mbx_tl_intg_err has 1 failures.
0.mbx_tl_intg_err.22585884147569678425470804166819692484849339100081246035470963236523916847099
Line 95, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 32594754 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x2795f2d8 a_data = 0xa8ac4cc4 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0x72 a_opcode = PutFullData a_user = 0x24abb d_data = 0x1f6207dc d_size = 0x1 d_param = 0x0 d_source = 0x5d d_opcode = AccessAck d_error = 0 d_user = 11111011001110 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 32594754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_csr_mem_rw_with_rand_reset has 1 failures.
0.mbx_csr_mem_rw_with_rand_reset.43784212159660969571822155396193623545566995315083766461256647830316631265783
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 1016518 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x8fb7d8d4 a_data = 0xdbb7a5a6 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0xf9 a_opcode = PutFullData a_user = 0x39567 d_data = 0x7a919a88 d_size = 0x3 d_param = 0x0 d_source = 0xe0 d_opcode = AccessAck d_error = 0 d_user = 1101000110101 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 1016518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutFullData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_errors.44790413372213150845806284053236002414167515374848572251512729179111843908792
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 2271711 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xf2990450 a_data = 0xbb9871d8 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0x5d a_opcode = PutFullData a_user = 0x3df11 d_data = 0xe1c85aee d_size = 0x2 d_param = 0x0 d_source = 0xff d_opcode = AccessAckData d_error = 0 d_user = 10001101101101 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 2271711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---