ROM_CTRL/64KB Simulation Results

Monday May 26 2025 17:08:21 UTC

GitHub Revision: 9bdf6bb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.510s 2.236ms 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 7.360s 2.111ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.690s 206.684us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 8.300s 3.107ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.960s 1.025ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 11.560s 620.240us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.690s 206.684us 1 1 100.00
rom_ctrl_csr_aliasing 7.960s 1.025ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.240s 699.254us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.640s 1.582ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 9.130s 382.537us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 24.720s 2.997ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 14.250s 551.499us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.320s 383.711us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 11.050s 296.187us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 11.050s 296.187us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 7.360s 2.111ms 1 1 100.00
rom_ctrl_csr_rw 7.690s 206.684us 1 1 100.00
rom_ctrl_csr_aliasing 7.960s 1.025ms 1 1 100.00
rom_ctrl_same_csr_outstanding 7.100s 1.340ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 7.360s 2.111ms 1 1 100.00
rom_ctrl_csr_rw 7.690s 206.684us 1 1 100.00
rom_ctrl_csr_aliasing 7.960s 1.025ms 1 1 100.00
rom_ctrl_same_csr_outstanding 7.100s 1.340ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 55.850s 1.796ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 38.310s 1.630ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.649m 466.836us 1 1 100.00
rom_ctrl_tl_intg_err 39.020s 303.727us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.649m 466.836us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.649m 466.836us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 55.850s 1.796ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 55.850s 1.796ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 55.850s 1.796ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 55.850s 1.796ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 55.850s 1.796ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.649m 466.836us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.649m 466.836us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.510s 2.236ms 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.510s 2.236ms 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.510s 2.236ms 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 39.020s 303.727us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 55.850s 1.796ms 1 1 100.00
rom_ctrl_kmac_err_chk 14.250s 551.499us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 55.850s 1.796ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 55.850s 1.796ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 55.850s 1.796ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 38.310s 1.630ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.649m 466.836us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 56.690s 1.834ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00