9bdf6bb| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 4.720s | 1.431ms | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 2.670s | 246.934us | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 2.320s | 271.175us | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 20.830s | 41.960ms | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 3.230s | 846.161us | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 44.740s | 22.730ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 2.500s | 1.708ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 10.260s | 17.353ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 1.353m | 74.272ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 2.190s | 372.455us | 1 | 1 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 3.430s | 952.183us | 1 | 1 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 1.780s | 132.149us | 1 | 1 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 1.590s | 60.012us | 0 | 1 | 0.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 1.810s | 235.473us | 1 | 1 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 1.920s | 444.466us | 1 | 1 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 2.040s | 83.659us | 1 | 1 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 1.770s | 245.229us | 1 | 1 | 100.00 |
| V1 | progbuf_busy | rv_dm_cmderr_busy | 2.190s | 372.455us | 1 | 1 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 1.740s | 102.022us | 1 | 1 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 2.240s | 570.349us | 1 | 1 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 1.780s | 132.149us | 1 | 1 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 1.620s | 164.494us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 3.290s | 128.162us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.930s | 202.032us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 53.860s | 25.390ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 18.700s | 2.347ms | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 2.780s | 185.199us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 18.700s | 2.347ms | 1 | 1 | 100.00 |
| rv_dm_csr_rw | 2.930s | 202.032us | 1 | 1 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 1.980s | 61.257us | 1 | 1 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 1.980s | 154.253us | 1 | 1 | 100.00 |
| V1 | TOTAL | 25 | 27 | 92.59 | |||
| V2 | idcode | rv_dm_smoke | 4.720s | 1.431ms | 1 | 1 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 2.290s | 349.536us | 1 | 1 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 2.980s | 602.451us | 1 | 1 | 100.00 |
| V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 1.990s | 111.740us | 1 | 1 | 100.00 |
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 2.150s | 316.700us | 1 | 1 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 15.090s | 6.570ms | 0 | 1 | 0.00 |
| rv_dm_delayed_resp_sba_tl_access | 1.820s | 82.161us | 0 | 1 | 0.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 10.850s | 4.946ms | 1 | 1 | 100.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 2.030s | 127.129us | 0 | 1 | 0.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 1.890s | 295.180us | 0 | 1 | 0.00 |
| V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 4.430s | 4.011ms | 1 | 1 | 100.00 |
| V2 | ndmreset_req | rv_dm_ndmreset_req | 3.360s | 937.341us | 1 | 1 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 1.500s | 108.069us | 0 | 1 | 0.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 27.470s | 13.828ms | 0 | 1 | 0.00 |
| rv_dm_tap_fsm_rand_reset | 1.860s | 85.790us | 0 | 1 | 0.00 | ||
| V2 | hartsel_warl | rv_dm_hartsel_warl | 1.640s | 82.400us | 1 | 1 | 100.00 |
| V2 | stress_all | rv_dm_stress_all | 2.180s | 2.296ms | 0 | 1 | 0.00 |
| V2 | alert_test | rv_dm_alert_test | 1.840s | 159.727us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 1.770s | 95.057us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 1.770s | 95.057us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 18.700s | 2.347ms | 1 | 1 | 100.00 |
| rv_dm_csr_hw_reset | 3.290s | 128.162us | 1 | 1 | 100.00 | ||
| rv_dm_csr_rw | 2.930s | 202.032us | 1 | 1 | 100.00 | ||
| rv_dm_same_csr_outstanding | 6.100s | 1.580ms | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 18.700s | 2.347ms | 1 | 1 | 100.00 |
| rv_dm_csr_hw_reset | 3.290s | 128.162us | 1 | 1 | 100.00 | ||
| rv_dm_csr_rw | 2.930s | 202.032us | 1 | 1 | 100.00 | ||
| rv_dm_same_csr_outstanding | 6.100s | 1.580ms | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 10 | 19 | 52.63 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 3.060s | 885.689us | 1 | 1 | 100.00 |
| rv_dm_tl_intg_err | 15.330s | 2.642ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 15.330s | 2.642ms | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 4.430s | 4.011ms | 1 | 1 | 100.00 |
| rv_dm_debug_disabled | 1.940s | 140.252us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | rv_dm_sba_debug_disabled | 4.430s | 4.011ms | 1 | 1 | 100.00 |
| rv_dm_debug_disabled | 1.940s | 140.252us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | rv_dm_smoke | 4.720s | 1.431ms | 1 | 1 | 100.00 |
| V2S | sec_cm_dm_en_ctrl_lc_gated | rv_dm_buffered_enable | 1.870s | 177.839us | 1 | 1 | 100.00 |
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 1.710s | 66.137us | 1 | 1 | 100.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 1.710s | 66.137us | 1 | 1 | 100.00 |
| V2S | sec_cm_exec_ctrl_mubi | rv_dm_buffered_enable | 1.870s | 177.839us | 1 | 1 | 100.00 |
| V2S | TOTAL | 5 | 5 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 1.710s | 20.314us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | rv_dm_scanmode | 9.825m | 300.000ms | 0 | 1 | 0.00 | |
| TOTAL | 40 | 53 | 75.47 |
Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
0.rv_dm_delayed_resp_sba_tl_access.107765603726847584158209439528733623418806769886193383235208023266853724730213
Line 127, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 143
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test rv_dm_autoincr_sba_tl_access has 1 failures.
0.rv_dm_autoincr_sba_tl_access.43639580685607584178018581543889341411599232927951431322060971357689898734803
Line 127, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 143
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs * [])` has 2 failures:
Test rv_dm_hart_unavail has 1 failures.
0.rv_dm_hart_unavail.31738779110453763341625380307235405707393336470598043967572553838930306107971
Line 72, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest/run.log
UVM_ERROR @ 108068661 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 108068661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 1 failures.
0.rv_dm_stress_all.59522945214606865102956472216234589099415624941921339954978545732904749873643
Line 77, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 2296125517 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2296125517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access has 1 failures:
0.rv_dm_tap_fsm.82280148929819609971960255744113363838540685117975180885036216959757221666971
Line 89, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_cip_lib_0/seq_lib/cip_base_vseq.sv, 304
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR (rv_dm_scoreboard.sv:413) [scoreboard] sba_tl_access_q item uncompared: has 1 failures:
0.rv_dm_sba_tl_access.28101451254297757790374486944501807032385410140997045659525131381789141751002
Line 81, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 6569757178 ps: (rv_dm_scoreboard.sv:413) [uvm_test_top.env.scoreboard] sba_tl_access_q item uncompared:
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5626
UVM_ERROR (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6985) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_tap_fsm_rand_reset.105532205347507353762885283810653297947628874752821562627744385266093591669694
Line 74, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 85790285 ps: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6985) { a_addr: 'h75c59554 a_data: 'h326231fa a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hf5 a_opcode: 'h4 a_user: 'h18783 d_param: 'h0 d_source: 'hf5 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 85790285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed gmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs * [])` has 1 failures:
0.rv_dm_mem_tl_access_resuming.10462678578498316277254779483040902276265512175201094105701282240568425085624
Line 72, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest/run.log
UVM_ERROR @ 60012396 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 60012396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 1 failures:
0.rv_dm_jtag_dmi_debug_disabled.107141007367083537075236357002042186264184787085113879497615650466825690403038
Line 72, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 295180026 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2232656630 [0x8513a2f6] vs 0 [0x0])
UVM_INFO @ 295180026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
0.rv_dm_scanmode.30187625836714737852413253419444165109625402665881045103618238331655286642975
Line 72, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_scanmode/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6017) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_stress_all_with_rand_reset.96514868870038146057760183727788459824524894542981346813069297074179249019769
Line 74, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 20313956 ps: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6017) { a_addr: 'h1f8d4674 a_data: 'hab7266ae a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hf1 a_opcode: 'h4 a_user: 'h1ba4f d_param: 'h0 d_source: 'hf1 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 20313956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@7573) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_tl_errors.36623283808765043358250062728507819749969292489628198853323610501056617367497
Line 73, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest/run.log
UVM_ERROR @ 95056595 ps: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@7573) { a_addr: 'hb35e37e0 a_data: 'hde78716d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h53 a_opcode: 'h4 a_user: 'h1bed6 d_param: 'h0 d_source: 'h53 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 95056595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@22897) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_csr_mem_rw_with_rand_reset.17062135115156212593855467514267315116927112470789013437947367789640009786092
Line 80, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 185198659 ps: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@22897) { a_addr: 'h2dc47758 a_data: 'h38fdef60 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h6 a_opcode: 'h4 a_user: 'h184e6 d_param: 'h0 d_source: 'h6 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 185198659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---