RV_TIMER Simulation Results

Monday May 26 2025 17:08:21 UTC

GitHub Revision: 9bdf6bb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.620s	24.431us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.460s	15.823us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.420s	43.524us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.880s	1.241ms	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.830s	79.063us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.910s	155.794us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.420s	43.524us	1	1	100.00
		rv_timer_csr_aliasing	1.830s	79.063us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.720s	133.429us	1	1	100.00
V2	disabled	rv_timer_disabled	3.800s	2.669ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	3.181m	385.319ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	3.181m	385.319ms	1	1	100.00
V2	stress	rv_timer_stress_all	3.370s	1.822ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.530s	46.474us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.490s	34.642us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.540s	2.448ms	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.540s	2.448ms	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.460s	15.823us	1	1	100.00
		rv_timer_csr_rw	1.420s	43.524us	1	1	100.00
		rv_timer_csr_aliasing	1.830s	79.063us	1	1	100.00
		rv_timer_same_csr_outstanding	1.660s	37.004us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.460s	15.823us	1	1	100.00
		rv_timer_csr_rw	1.420s	43.524us	1	1	100.00
		rv_timer_csr_aliasing	1.830s	79.063us	1	1	100.00
		rv_timer_same_csr_outstanding	1.660s	37.004us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.930s	404.260us	1	1	100.00
		rv_timer_tl_intg_err	1.930s	131.795us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.930s	131.795us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	28.670s	3.704ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.510s	73.520us	1	1	100.00
		rv_timer_max	1.620s	29.055us	1	1	100.00
		TOTAL			19	19	100.00