SPI_DEVICE/1R1W Simulation Results

Monday May 26 2025 17:08:21 UTC

GitHub Revision: 9bdf6bb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	4.431m	43.482ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.120s	554.623us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.540s	32.434us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	18.000s	5.015ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.770s	3.964ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.080s	159.160us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.540s	32.434us	1	1	100.00
		spi_device_csr_aliasing	15.770s	3.964ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.720s	12.824us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.760s	279.288us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.790s	87.013us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.620s	4.497us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.830s	4.070us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.590s	116.919us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.590s	116.919us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	7.090s	1.669ms	1	1	100.00
		spi_device_tpm_sts_read	1.750s	80.092us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	15.340s	5.051ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	8.890s	12.604ms	1	1	100.00
		spi_device_flash_all	3.063m	203.465ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	7.390s	2.726ms	1	1	100.00
		spi_device_flash_all	3.063m	203.465ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	7.390s	2.726ms	1	1	100.00
		spi_device_flash_all	3.063m	203.465ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	3.063m	203.465ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.550s	236.592us	1	1	100.00
		spi_device_flash_all	3.063m	203.465ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.550s	236.592us	1	1	100.00
		spi_device_flash_all	3.063m	203.465ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.550s	236.592us	1	1	100.00
		spi_device_flash_all	3.063m	203.465ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.550s	236.592us	1	1	100.00
		spi_device_flash_all	3.063m	203.465ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.550s	236.592us	1	1	100.00
		spi_device_flash_all	3.063m	203.465ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	16.190s	6.217ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	8.220s	1.555ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	8.220s	1.555ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	8.220s	1.555ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	6.460s	2.019ms	1	1	100.00
		spi_device_read_buffer_direct	5.020s	781.406us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	8.220s	1.555ms	1	1	100.00
		spi_device_flash_all	3.063m	203.465ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	3.063m	203.465ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	3.063m	203.465ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.510s	496.769us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.510s	496.769us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	4.431m	43.482ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.477m	64.972ms	1	1	100.00
V2	stress_all	spi_device_stress_all	4.475m	153.445ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.690s	33.270us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.850s	48.369us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.710s	843.476us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.710s	843.476us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.120s	554.623us	1	1	100.00
		spi_device_csr_rw	2.540s	32.434us	1	1	100.00
		spi_device_csr_aliasing	15.770s	3.964ms	1	1	100.00
		spi_device_same_csr_outstanding	4.050s	3.079ms	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.120s	554.623us	1	1	100.00
		spi_device_csr_rw	2.540s	32.434us	1	1	100.00
		spi_device_csr_aliasing	15.770s	3.964ms	1	1	100.00
		spi_device_same_csr_outstanding	4.050s	3.079ms	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.250s	516.369us	1	1	100.00
		spi_device_tl_intg_err	6.310s	332.617us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.310s	332.617us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	4.432m	63.203ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.64187403636843196749432846255860553588988389028883391230373058565599881464455
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3747018 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[63])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3747018 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3747018 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[959])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.32887768647898403763094154482375812571926591767262730720480193105391904524
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1802288 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7f1c2 [1111111000111000010] vs 0x0 [0])
        UVM_ERROR @   1813288 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9c8975 [100111001000100101110101] vs 0x0 [0])
        UVM_ERROR @   1874288 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7b0b74 [11110110000101101110100] vs 0x0 [0])
        UVM_ERROR @   1947288 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x64d3fd [11001001101001111111101] vs 0x0 [0])
        UVM_ERROR @   2016288 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe12225 [111000010010001000100101] vs 0x0 [0])