SPI_HOST Simulation Results

Monday May 26 2025 17:08:21 UTC

GitHub Revision: 9bdf6bb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.483m	5.036ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	114.079us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	68.280us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	167.589us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	38.110us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	61.804us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	68.280us	1	1	100.00
		spi_host_csr_aliasing	4.000s	38.110us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	15.879us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	51.384us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	11.000s	47.018us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	9.000s	255.716us	1	1	100.00
		spi_host_error_cmd	8.000s	32.655us	1	1	100.00
		spi_host_event	13.000s	11.593ms	1	1	100.00
V2	clock_rate	spi_host_speed	12.000s	81.490us	1	1	100.00
V2	speed	spi_host_speed	12.000s	81.490us	1	1	100.00
V2	chip_select_timing	spi_host_speed	12.000s	81.490us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	15.000s	287.786us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	47.648us	1	1	100.00
V2	cpol_cpha	spi_host_speed	12.000s	81.490us	1	1	100.00
V2	full_cycle	spi_host_speed	12.000s	81.490us	1	1	100.00
V2	duplex	spi_host_smoke	1.483m	5.036ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	1.483m	5.036ms	1	1	100.00
V2	stress_all	spi_host_stress_all	1.617m	13.917ms	1	1	100.00
V2	spien	spi_host_spien	5.000s	209.272us	1	1	100.00
V2	stall	spi_host_status_stall	16.000s	1.336ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	14.000s	688.806us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	9.000s	255.716us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	19.971us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	15.247us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	128.341us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	128.341us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	114.079us	1	1	100.00
		spi_host_csr_rw	4.000s	68.280us	1	1	100.00
		spi_host_csr_aliasing	4.000s	38.110us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	18.555us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	114.079us	1	1	100.00
		spi_host_csr_rw	4.000s	68.280us	1	1	100.00
		spi_host_csr_aliasing	4.000s	38.110us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	18.555us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	49.116us	1	1	100.00
		spi_host_sec_cm	4.000s	527.856us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	49.116us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	1.683m	5.825ms	1	1	100.00
		TOTAL			26	26	100.00