SRAM_CTRL/MAIN Simulation Results

Monday May 26 2025 17:08:21 UTC

GitHub Revision: 9bdf6bb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	15.780s	3.226ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.660s	111.442us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.580s	29.850us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.340s	348.273us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.660s	20.494us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.620s	1.286ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.580s	29.850us	1	1	100.00
		sram_ctrl_csr_aliasing	1.660s	20.494us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.479m	10.722ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.523m	6.572ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	14.539m	19.560ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.651m	2.596ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	23.503m	55.737ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.086m	76.508ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	43.270s	60.097ms	1	1	100.00
V2	executable	sram_ctrl_executable	11.751m	33.253ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	13.160s	1.721ms	1	1	100.00
		sram_ctrl_partial_access_b2b	2.606m	8.463ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	5.120s	1.290ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	4.660s	671.648us	1	1	100.00
		sram_ctrl_throughput_w_readback	1.035m	943.833us	1	1	100.00
V2	regwen	sram_ctrl_regwen	1.927m	1.308ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.940s	681.543us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	39.046m	183.606ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.630s	34.645us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.070s	73.506us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.070s	73.506us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.660s	111.442us	1	1	100.00
		sram_ctrl_csr_rw	1.580s	29.850us	1	1	100.00
		sram_ctrl_csr_aliasing	1.660s	20.494us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.670s	28.051us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.660s	111.442us	1	1	100.00
		sram_ctrl_csr_rw	1.580s	29.850us	1	1	100.00
		sram_ctrl_csr_aliasing	1.660s	20.494us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.670s	28.051us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	33.000s	7.193ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.720s	4.259us	0	1	0.00
		sram_ctrl_tl_intg_err	2.080s	168.295us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.720s	4.259us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.080s	168.295us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1.927m	1.308ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1.927m	1.308ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.580s	29.850us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	11.751m	33.253ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	11.751m	33.253ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	11.751m	33.253ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	43.270s	60.097ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.460s	900.974us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	33.000s	7.193ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.650s	2.651ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	15.780s	3.226ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	15.780s	3.226ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	11.751m	33.253ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.720s	4.259us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	43.270s	60.097ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.720s	4.259us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.720s	4.259us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	15.780s	3.226ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.720s	4.259us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.609m	10.817ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.92459725658938174046074407055860455088814361161510852453425408393194471957163
      Line 102, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4258775 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4258775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---