SRAM_CTRL/RET Simulation Results

Monday May 26 2025 17:08:21 UTC

GitHub Revision: 9bdf6bb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	14.790s	990.430us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.620s	139.061us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.700s	33.291us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.720s	458.294us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.640s	13.695us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.390s	216.124us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.700s	33.291us	1	1	100.00
		sram_ctrl_csr_aliasing	1.640s	13.695us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.420s	468.706us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.960s	807.618us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	1.018m	3.491ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.166m	15.462ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	37.970s	3.295ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.976m	5.664ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.800s	5.869ms	1	1	100.00
V2	executable	sram_ctrl_executable	19.968m	79.714ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	1.005m	1.266ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.146m	35.353ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	10.940s	293.614us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	1.024m	724.820us	1	1	100.00
		sram_ctrl_throughput_w_readback	1.028m	1.115ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	1.357m	879.760us	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.720s	29.290us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	4.108m	10.277ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.540s	43.656us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.890s	160.052us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.890s	160.052us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.620s	139.061us	1	1	100.00
		sram_ctrl_csr_rw	1.700s	33.291us	1	1	100.00
		sram_ctrl_csr_aliasing	1.640s	13.695us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.770s	295.075us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.620s	139.061us	1	1	100.00
		sram_ctrl_csr_rw	1.700s	33.291us	1	1	100.00
		sram_ctrl_csr_aliasing	1.640s	13.695us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.770s	295.075us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.690s	651.825us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.820s	10.421us	0	1	0.00
		sram_ctrl_tl_intg_err	2.990s	244.672us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.820s	10.421us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.990s	244.672us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1.357m	879.760us	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1.357m	879.760us	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.700s	33.291us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	19.968m	79.714ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	19.968m	79.714ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	19.968m	79.714ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.800s	5.869ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.260s	37.174us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.690s	651.825us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.360s	32.286us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	14.790s	990.430us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	14.790s	990.430us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	19.968m	79.714ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.820s	10.421us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.800s	5.869ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.820s	10.421us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.820s	10.421us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	14.790s	990.430us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.820s	10.421us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.190m	1.577ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.23939203000755817435219108485820765399612414587127373249217155750378981263429
      Line 96, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  10420671 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  10420671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---