UART Simulation Results

Monday May 26 2025 17:08:21 UTC

GitHub Revision: 9bdf6bb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.370s	494.322us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.540s	24.037us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.470s	80.752us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.700s	178.249us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.630s	27.030us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.620s	62.546us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.470s	80.752us	1	1	100.00
		uart_csr_aliasing	1.630s	27.030us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	7.310s	38.802ms	1	1	100.00
V2	parity	uart_smoke	2.370s	494.322us	1	1	100.00
		uart_tx_rx	7.310s	38.802ms	1	1	100.00
V2	parity_error	uart_intr	8.030s	26.060ms	1	1	100.00
		uart_rx_parity_err	32.090s	34.182ms	1	1	100.00
V2	watermark	uart_tx_rx	7.310s	38.802ms	1	1	100.00
		uart_intr	8.030s	26.060ms	1	1	100.00
V2	fifo_full	uart_fifo_full	7.160m	306.228ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	10.430s	52.646ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	21.270s	49.838ms	1	1	100.00
V2	rx_frame_err	uart_intr	8.030s	26.060ms	1	1	100.00
V2	rx_break_err	uart_intr	8.030s	26.060ms	1	1	100.00
V2	rx_timeout	uart_intr	8.030s	26.060ms	1	1	100.00
V2	perf	uart_perf	6.860m	20.724ms	1	1	100.00
V2	sys_loopback	uart_loopback	4.210s	7.768ms	1	1	100.00
V2	line_loopback	uart_loopback	4.210s	7.768ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	31.370s	64.300ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.000s	4.677ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.750s	871.657us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	11.680s	7.043ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	10.274m	145.721ms	1	1	100.00
V2	stress_all	uart_stress_all	4.090m	308.551ms	1	1	100.00
V2	alert_test	uart_alert_test	1.540s	13.252us	1	1	100.00
V2	intr_test	uart_intr_test	1.620s	38.366us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.070s	113.636us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.070s	113.636us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.540s	24.037us	1	1	100.00
		uart_csr_rw	1.470s	80.752us	1	1	100.00
		uart_csr_aliasing	1.630s	27.030us	1	1	100.00
		uart_same_csr_outstanding	1.550s	20.011us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.540s	24.037us	1	1	100.00
		uart_csr_rw	1.470s	80.752us	1	1	100.00
		uart_csr_aliasing	1.630s	27.030us	1	1	100.00
		uart_same_csr_outstanding	1.550s	20.011us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.630s	113.252us	1	1	100.00
		uart_tl_intg_err	2.130s	104.822us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.130s	104.822us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	41.730s	3.182ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00