CHIP Simulation Results

Monday May 26 2025 17:08:21 UTC

GitHub Revision: `9bdf6bb`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	4.401m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	4.401m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	3.108m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.943m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.699m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.406m	4.743ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.406m	4.743ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.406m	4.743ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	38.150s	10.380us	0	1	0.00
		chip_sw_example_manufacturer	5.051m		0	1	0.00
		chip_sw_example_concurrency	4.131m	4.303ms	1	1	100.00
		chip_sw_uart_smoketest_signed	12.611s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	9.480s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	9.720s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	9.720s		0	1	0.00
V1	xbar_smoke	xbar_smoke	8.890s	11.928us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	3.222m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	10.872m	9.706ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.359m	5.123ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	1.705m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	1.170m		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.932m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.495m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.380s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.380s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	4.379m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	4.340m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	4.439m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	4.439m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.631m	4.160ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.208m	5.310ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.314m	14.712ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	15.461s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.592s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	12.417m	20.265ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.814m	6.144ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	21.933m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	21.933m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	19.424s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.402m	5.079ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.402m	5.079ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.006m	18.025ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.169m	4.544ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.035m	5.536ms	1	1	100.00
		chip_sw_aes_idle	4.863m	5.116ms	1	1	100.00
		chip_sw_hmac_enc_idle	5.465m	5.817ms	1	1	100.00
		chip_sw_kmac_idle	4.484m	4.279ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	13.912m	11.719ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	11.144m	12.022ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	11.001m	12.024ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	12.222m	12.015ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	15.709s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.884s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.754s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.644s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.437s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.758s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.591s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	15.709s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.884s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.754s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.644s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.437s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.758s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.591s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.817s		0	1	0.00
		chip_sw_aes_enc_jitter_en	47.130s	10.240us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	45.930s	10.120us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	46.240s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	50.910s	10.340us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.464s		0	1	0.00
		chip_sw_clkmgr_jitter	4.265m	4.519ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.847m	3.591ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	15.638s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	47.170s	10.280us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	47.590s	10.160us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	47.270s	10.100us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	51.370s	10.180us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	46.620s	10.300us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.645s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	10.828s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.123s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.203s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	18.549m	16.348ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.372m	13.509ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.402m	5.079ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	18.721s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.372m	13.509ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	14.120s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	26.266s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	28.957s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	28.977s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	30.542s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	18.549m	16.348ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.314m	14.712ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	21.241m	20.024ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.801m	6.624ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	7.339m	9.241ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.280m	4.031ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	18.549m	16.348ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	12.107s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.731s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	18.549m	16.348ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	11.581s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	7.339m	9.241ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	14.089s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	13.377s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	13.259s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	12.831s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.391s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	13.582s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.731s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	53.912s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	1.293m		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	53.912s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	53.912s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	53.912s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	5.759m	5.474ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	17.890s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	17.522s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	17.694s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	37.187s		0	1	0.00
		chip_sw_lc_ctrl_transition	53.912s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.040m	6.959ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	7.611m	14.680ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.520s		0	1	0.00
		chip_prim_tl_access	17.181m	26.117ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	15.709s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.884s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.754s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.644s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.437s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.758s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.591s		0	1	0.00
		chip_rv_dm_lc_disabled	12.417m	20.265ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.276m	4.620ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	47.130s	10.240us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.700m	3.374ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.863m	5.116ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.363m	4.733ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	45.930s	10.120us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.465m	5.817ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.871m	5.514ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.417m	4.692ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	50.910s	10.340us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.040m	6.959ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	53.912s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	39.850s	10.320us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.399m	4.549ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.484m	4.279ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.383s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.383s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.391s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.258m	3.905ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	11.155s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.040m	6.959ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	46.240s	10.240us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	11.967s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	10.817s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.035m	5.536ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.035m	5.536ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.035m	5.536ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.030m	5.617ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	7.611m	14.680ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	7.611m	14.680ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.198m	6.756ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.464s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.520s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	18.549m	16.348ms	1	1	100.00
		chip_sw_data_integrity_escalation	4.439m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	53.912s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.030m	5.617ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.040m	6.959ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.198m	6.756ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.886m	4.993ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.030m	5.617ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.040m	6.959ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.198m	6.756ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.886m	4.993ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	53.912s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.442s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	1.293m		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	17.890s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	17.522s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	17.694s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	37.187s		0	1	0.00
		chip_sw_lc_ctrl_transition	53.912s		0	1	0.00
		chip_prim_tl_access	17.181m	26.117ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	17.181m	26.117ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	22.377s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	24.309s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	10.828s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.817s		0	1	0.00
		chip_sw_aes_enc_jitter_en	47.130s	10.240us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	45.930s	10.120us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	46.240s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	50.910s	10.340us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.464s		0	1	0.00
		chip_sw_clkmgr_jitter	4.265m	4.519ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	6.564m	7.206ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	6.564m	7.206ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	3.960m	3.660ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.435m	3.097ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	6.167m	5.395ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.842m	4.848ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.602m	3.665ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.552m	5.664ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.886m	4.993ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	21.241m	20.024ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	21.241m	20.024ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.471m	4.137ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.306m	4.933ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.314m	3.907ms	1	1	100.00
		chip_sw_csrng_smoketest	3.037m	3.153ms	1	1	100.00
		chip_sw_gpio_smoketest	4.341m	5.325ms	1	1	100.00
		chip_sw_hmac_smoketest	4.219m	4.281ms	1	1	100.00
		chip_sw_kmac_smoketest	4.472m	5.588ms	1	1	100.00
		chip_sw_otbn_smoketest	5.548m	5.434ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.136m	4.705ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.111m	4.902ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.279m	5.159ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.130m	3.775ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.888m	4.963ms	1	1	100.00
		chip_sw_uart_smoketest	3.257m	3.969ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	13.473s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	12.611s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.222m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	14.461s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.838m	6.176ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.904m	4.226ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.258m	6.394ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.901m	5.510ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	11.335s		0	1	0.00
		chip_rv_dm_lc_disabled	12.417m	20.265ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	12.865s		0	1	0.00
		chip_sw_lc_walkthrough_prod	15.315s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	18.886s		0	1	0.00
		chip_sw_lc_walkthrough_rma	18.475s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	11.335s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	52.509s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	13.329s		0	1	0.00
		rom_volatile_raw_unlock	10.937s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.911s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.282m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.310m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.697m	5.129ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.697m	5.129ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	9.720s		0	1	0.00
		chip_same_csr_outstanding	13.340s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	9.720s		0	1	0.00
		chip_same_csr_outstanding	13.340s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	3.352m	504.878us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.940s	12.667us	1	1	100.00
		xbar_smoke_large_delays	5.518m	3.100ms	1	1	100.00
		xbar_smoke_slow_rsp	5.366m	2.042ms	1	1	100.00
		xbar_random_zero_delays	32.070s	28.661us	1	1	100.00
		xbar_random_large_delays	23.867m	12.667ms	1	1	100.00
		xbar_random_slow_rsp	17.044m	6.281ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	32.590s	56.682us	1	1	100.00
		xbar_error_and_unmapped_addr	14.670s	17.875us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	22.870s	34.797us	1	1	100.00
		xbar_error_and_unmapped_addr	14.670s	17.875us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	4.279m	736.938us	1	1	100.00
		xbar_access_same_device_slow_rsp	11.058m	4.314ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.518m	249.478us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	7.373m	418.923us	1	1	100.00
		xbar_stress_all_with_error	18.298m	3.568ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	16.046m	694.807us	1	1	100.00
		xbar_stress_all_with_reset_error	4.722m	413.311us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	12.763s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	14.528s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.450s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	14.893s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	13.871s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.689s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	13.073s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	12.240s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.209s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.638s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	12.407s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.540s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.326s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	13.997s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	12.776s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	11.081s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.490s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	11.871s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	12.619s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	14.419s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.148s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.155s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.822s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	11.942s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.270s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	13.498s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.331s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	13.052s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	13.130s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	13.258s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	13.955s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.233s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.394s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.483s		0	1	0.00
		rom_e2e_asm_init_dev	11.720s		0	1	0.00
		rom_e2e_asm_init_prod	12.077s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.719s		0	1	0.00
		rom_e2e_asm_init_rma	11.391s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.189s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.396s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.564s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.551s		0	1	0.00
V2		TOTAL			66	205	32.20
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.125m	5.558ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.718m	4.075ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.696s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.314s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.413s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.708s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	18.549m	16.348ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	11.004s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	18.241m	16.712ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	20.371s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	11.307s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.696s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.314s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.413s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.005s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.743s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.284s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	51.192s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	20.774m	13.430ms	1	1	100.00
		chip_plic_all_irqs_0	9.267m	6.957ms	1	1	100.00
		chip_plic_all_irqs_10	9.824m	6.560ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.603m	4.755ms	1	1	100.00
		chip_sw_dma_abort	4.520m	5.506ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.773s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.317s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.655s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.480s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.980s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.784s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.759s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.656s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.682s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.580s		0	1	0.00
		chip_sw_mbx_smoketest	4.300m	4.117ms	1	1	100.00
		TOTAL			77	247	31.17

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.50857693611186794247094037403996605013141714637301282322866078957500012344746
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (8acc23)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 286.891s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.75418503755497542897543410184625549865039784586719049424531302671328284783689
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (a8b1b0)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 256.347s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.9405654071808069761523045840091834578788055108695565490451044409318379745425
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (d1014d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 252.810s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.4052127291031583397497592831331936278432256786520267711050138154686324523452
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (94daf7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 250.497s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.30427128935251973436757285989778836398467948902669561190800941119648212805849
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (6f7d0f)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 254.306s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.31076585549895570255019845696764531509722142451911102985728013084986629846237
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.57678602862725255502143508765392539796067498320085314872452967595877584954336
    Line 437, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.13089880407804398294579511910969678445644143076158554339135820880674856188638
    Line 437, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.93415924185731566770844004785758552420068991872782302517387538866704102618154
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.34930335008186480680360679549427980559841187921853732682489525165069718659787
    Line 432, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.75149932863311939645754923768769828781525387571963097393970550469924073958571
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.17575381610896778834339419324876891640522880691667116471204284757132128787837
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.35390710538374284482585989294736120198266653922631312570558116015644866751542
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.102361953382520031574267651055867049903403214532004395844738315472206824301821
Line 514, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20024.212456 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20024.212456 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.38870874852711155381225439100119073073629506699555881116755673204720439518935
Line 459, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18017.873586 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18017.873586 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.105702458502090351220902484662689929324612033430395562802682791816713816352802
Line 449, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18024.694756 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18024.694756 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.107093844974359069090484386279508745306460300403240157959899088022936484750736
Line 442, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12022.311524 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12022.311524 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.79885158482154524299394766645029953164472069408447954231592446273947295507708
Line 431, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12023.525158 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12023.525158 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.44574854728017924620061159258149035719779355430509460891101977049171476560044
Line 434, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12015.170882 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12015.170882 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.71374187205605628074175927161147844211327898845162234555926390807158040466443
Line 482, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 6958.743016 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (2562762873080332465542310517218094183523918647045881025094125671149243379302 [0x5aa78ee1da6fe4c35029576d3ae86920b5d171113f90117314cd4185e82ae66] vs 68773411755351791709353068195569560599280923354683207484603654727794650892347 [0x980c5f22ddf9ebf3c1bff251bd45302044d75b869277338b20d1c358aec9c83b])
  UVM_INFO @ 6958.743016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.48854948720641853286587438965495764169493977126842744457067472427134939246949
Line 504, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 5474.471752 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (106809462433716908006406059618959111342975720750773059484926565847911936558688 [0xec24036e1b8b901fa6bc391a6fae99656542ab7648d8489cad0ecfa211180660] vs 113794974711146560048446177774641162812208196118827331378457327619082820401546 [0xfb95ac5928b71a6a5beb5685319cd7888032e5b1025d7acbc33fc95499ea398a])
  UVM_INFO @ 5474.471752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.80120955703092532035277857393022901001592623813644658933997244650539822793488
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4160.254358 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h2ba5837e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h5  a_opcode: 'h1  a_user: 'h24885  d_param: 'h0  d_source: 'h5  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4160.254358 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.6367715157521395081488579568937646487714601010924996292446756165636854727469
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 5310.288963 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h1481878d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha  a_opcode: 'h0  a_user: 'h2695e  d_param: 'h0  d_source: 'ha  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5310.288963 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.99300404027525828656752906586985636103460448362471039581564752888592639654912
    Line 806, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.59827625028099188100600511451944680039893162125411302550701112705644124761450
    Line 515, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5122.806864 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5122.806864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.2930730355677585803670059906489929526986154077015867117955017862401128978181
    Line 734, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 9240.699980 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 9240.699980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.1770896058350267023453117949830035410886587258276051718486040209728776930622
    Line 465, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 3660.298800 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3660.298800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.98840800704157484582924940171967093138783933635365806406633355694650647896047
    Line 447, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 3096.847336 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 3096.847336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.33085074639124624141514234665982722826557537961859517904647121850051926472801
    Line 465, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 5078.697320 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 5078.697320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.38937121022593108816231875896305625626256965157361238870477378367825279903434
    Line 423, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 4848.359664 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 4848.359664 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.102905524438446981787335457848002714374117632112568623992603087105397243098736
    Line 431, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@36656) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.49651282533379755412672476970248217730727063662748063917514110566020448445889
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 5128.636944 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@36656) { a_addr: 'h2212  a_data: 'h1fe0f683  a_mask: 'h4  a_size: 'h1  a_param: 'h0  a_source: 'h50  a_opcode: 'h4  a_user: 'h2482d  d_param: 'h0  d_source: 'h50  d_data: 'h0  d_size: 'h1  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'h12a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5128.636944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.67416883659921918619449868489657570670175502291950424227342190336618447507697
    Line 401, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14712.348712 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14712.348712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.21827252941180702053140915281760973541911795172114848315006379611808212189294
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.12870267050800700662438717920970367535309213585502345286728715569343312900484
    Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5505.591816 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5505.591816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```