DMA Simulation Results

Tuesday May 27 2025 17:01:21 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	354.227us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	309.953us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	8.000s	1.648ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	17.744us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	277.048us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	8.000s	603.230us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	7.000s	261.341us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	150.993us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	277.048us	1	1	100.00
		dma_csr_aliasing	7.000s	261.341us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.733m	12.100ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	7.017m	40.628ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	2.283m	25.115ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	6.750m	36.011ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	7.017m	40.628ms	1	1	100.00
V2	dma_abort	dma_abort	13.000s	594.624us	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.650m	9.083ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	53.245us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	249.865us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	249.865us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	17.744us	1	1	100.00
		dma_csr_rw	4.000s	277.048us	1	1	100.00
		dma_csr_aliasing	7.000s	261.341us	1	1	100.00
		dma_same_csr_outstanding	5.000s	130.980us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	17.744us	1	1	100.00
		dma_csr_rw	4.000s	277.048us	1	1	100.00
		dma_csr_aliasing	7.000s	261.341us	1	1	100.00
		dma_same_csr_outstanding	5.000s	130.980us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	30.000s	366.195us	1	1	100.00
		dma_generic_stress	6.750m	36.011ms	1	1	100.00
		dma_handshake_stress	7.017m	40.628ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	7.000s	185.045us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	2.683m	54.693ms	1	1	100.00
		dma_longer_transfer	5.000s	214.299us	1	1	100.00
		TOTAL			21	21	100.00