EDN Simulation Results

Tuesday May 27 2025 17:01:21 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.910s	25.162us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.810s	15.969us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.750s	43.197us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.740s	719.310us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	2.020s	29.381us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.670s	31.646us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.750s	43.197us	1	1	100.00
		edn_csr_aliasing	2.020s	29.381us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.360s	57.332us	1	1	100.00
V2	csrng_commands	edn_genbits	2.360s	57.332us	1	1	100.00
V2	genbits	edn_genbits	2.360s	57.332us	1	1	100.00
V2	interrupts	edn_intr	2.110s	21.540us	1	1	100.00
V2	alerts	edn_alert	2.100s	33.966us	1	1	100.00
V2	errs	edn_err	2.280s	19.775us	1	1	100.00
V2	disable	edn_disable	1.580s	10.618us	1	1	100.00
		edn_disable_auto_req_mode	1.800s	182.136us	1	1	100.00
V2	stress_all	edn_stress_all	4.290s	352.764us	1	1	100.00
V2	intr_test	edn_intr_test	1.910s	27.048us	1	1	100.00
V2	alert_test	edn_alert_test	1.900s	17.809us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.860s	200.275us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.860s	200.275us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.810s	15.969us	1	1	100.00
		edn_csr_rw	1.750s	43.197us	1	1	100.00
		edn_csr_aliasing	2.020s	29.381us	1	1	100.00
		edn_same_csr_outstanding	2.180s	69.915us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.810s	15.969us	1	1	100.00
		edn_csr_rw	1.750s	43.197us	1	1	100.00
		edn_csr_aliasing	2.020s	29.381us	1	1	100.00
		edn_same_csr_outstanding	2.180s	69.915us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	3.990s	462.865us	1	1	100.00
		edn_tl_intg_err	3.590s	356.831us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.650s	22.153us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	2.100s	33.966us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	3.990s	462.865us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	3.990s	462.865us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	3.990s	462.865us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	3.990s	462.865us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	2.100s	33.966us	1	1	100.00
		edn_sec_cm	3.990s	462.865us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	2.100s	33.966us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.590s	356.831us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	37.900s	9.140ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00