HMAC Simulation Results

Tuesday May 27 2025 17:01:21 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 2.590s 67.032us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.660s 163.827us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.470s 54.974us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 8.370s 1.689ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.060s 114.303us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 5.764m 69.796ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.470s 54.974us 1 1 100.00
hmac_csr_aliasing 3.060s 114.303us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 47.350s 2.421ms 1 1 100.00
V2 back_pressure hmac_back_pressure 40.660s 17.922ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.164m 5.611ms 1 1 100.00
hmac_test_sha384_vectors 19.720s 503.779us 1 1 100.00
hmac_test_sha512_vectors 6.571m 128.771ms 1 1 100.00
hmac_test_hmac256_vectors 8.660s 266.381us 1 1 100.00
hmac_test_hmac384_vectors 10.270s 1.152ms 1 1 100.00
hmac_test_hmac512_vectors 11.610s 1.338ms 1 1 100.00
V2 burst_wr hmac_burst_wr 21.130s 578.195us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 1.165m 2.526ms 1 1 100.00
V2 error hmac_error 1.209m 5.396ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.611m 5.559ms 1 1 100.00
V2 save_and_restore hmac_smoke 2.590s 67.032us 1 1 100.00
hmac_long_msg 47.350s 2.421ms 1 1 100.00
hmac_back_pressure 40.660s 17.922ms 1 1 100.00
hmac_datapath_stress 1.165m 2.526ms 1 1 100.00
hmac_burst_wr 21.130s 578.195us 1 1 100.00
hmac_stress_all 3.985m 18.554ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 2.590s 67.032us 1 1 100.00
hmac_long_msg 47.350s 2.421ms 1 1 100.00
hmac_back_pressure 40.660s 17.922ms 1 1 100.00
hmac_datapath_stress 1.165m 2.526ms 1 1 100.00
hmac_wipe_secret 1.611m 5.559ms 1 1 100.00
hmac_test_sha256_vectors 3.164m 5.611ms 1 1 100.00
hmac_test_sha384_vectors 19.720s 503.779us 1 1 100.00
hmac_test_sha512_vectors 6.571m 128.771ms 1 1 100.00
hmac_test_hmac256_vectors 8.660s 266.381us 1 1 100.00
hmac_test_hmac384_vectors 10.270s 1.152ms 1 1 100.00
hmac_test_hmac512_vectors 11.610s 1.338ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 2.590s 67.032us 1 1 100.00
hmac_long_msg 47.350s 2.421ms 1 1 100.00
hmac_back_pressure 40.660s 17.922ms 1 1 100.00
hmac_datapath_stress 1.165m 2.526ms 1 1 100.00
hmac_burst_wr 21.130s 578.195us 1 1 100.00
hmac_error 1.209m 5.396ms 1 1 100.00
hmac_wipe_secret 1.611m 5.559ms 1 1 100.00
hmac_test_sha256_vectors 3.164m 5.611ms 1 1 100.00
hmac_test_sha384_vectors 19.720s 503.779us 1 1 100.00
hmac_test_sha512_vectors 6.571m 128.771ms 1 1 100.00
hmac_test_hmac256_vectors 8.660s 266.381us 1 1 100.00
hmac_test_hmac384_vectors 10.270s 1.152ms 1 1 100.00
hmac_test_hmac512_vectors 11.610s 1.338ms 1 1 100.00
hmac_stress_all 3.985m 18.554ms 1 1 100.00
V2 stress_all hmac_stress_all 3.985m 18.554ms 1 1 100.00
V2 alert_test hmac_alert_test 1.440s 15.132us 1 1 100.00
V2 intr_test hmac_intr_test 1.510s 45.514us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.380s 305.461us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.380s 305.461us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.660s 163.827us 1 1 100.00
hmac_csr_rw 1.470s 54.974us 1 1 100.00
hmac_csr_aliasing 3.060s 114.303us 1 1 100.00
hmac_same_csr_outstanding 2.380s 38.818us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.660s 163.827us 1 1 100.00
hmac_csr_rw 1.470s 54.974us 1 1 100.00
hmac_csr_aliasing 3.060s 114.303us 1 1 100.00
hmac_same_csr_outstanding 2.380s 38.818us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.870s 95.332us 1 1 100.00
hmac_tl_intg_err 3.050s 872.488us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.050s 872.488us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 2.590s 67.032us 1 1 100.00
V3 stress_reset hmac_stress_reset 2.740s 92.726us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.525m 6.111ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.610s 14.082us 1 1 100.00
TOTAL 28 28 100.00