I2C Simulation Results

Tuesday May 27 2025 17:01:21 UTC

GitHub Revision: `872a98e`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	27.790s	1.984ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	26.390s	1.218ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.660s	155.096us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.660s	70.050us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.960s	742.115us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.420s	94.500us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.820s	108.473us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.660s	70.050us	1	1	100.00
		i2c_csr_aliasing	2.420s	94.500us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.650s	145.931us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	2.888m	62.503ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	11.470s	1.259ms	1	1	100.00
V2	host_override	i2c_host_override	1.730s	71.595us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.279m	4.357ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.419m	2.017ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.900s	273.749us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.280s	696.135us	1	1	100.00
		i2c_host_fifo_reset_rx	6.050s	142.295us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.884m	5.480ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	6.990s	6.102ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.940s	324.388us	1	1	100.00
V2	target_glitch	i2c_target_glitch	7.310s	17.468ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	2.768m	25.250ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.640s	566.157us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	16.050s	984.736us	1	1	100.00
		i2c_target_intr_smoke	3.760s	646.072us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.890s	376.274us	1	1	100.00
		i2c_target_fifo_reset_tx	1.920s	623.638us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	6.360s	15.376ms	1	1	100.00
		i2c_target_stress_rd	16.050s	984.736us	1	1	100.00
		i2c_target_intr_stress_wr	2.510s	6.071ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.540s	2.667ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	2.370s	1.916ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.580s	1.672ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	20.390s	10.051ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.730s	533.922us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.810s	295.536us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	11.470s	1.259ms	1	1	100.00
		i2c_host_perf_precise	2.340s	285.951us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	6.990s	6.102ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	13.550s	1.671ms	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.060s	1.763ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.600s	480.294us	1	1	100.00
		i2c_target_nack_txstretch	2.060s	672.325us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.310s	1.525ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.550s	450.908us	1	1	100.00
V2	alert_test	i2c_alert_test	1.310s	26.677us	1	1	100.00
V2	intr_test	i2c_intr_test	1.660s	63.773us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.500s	335.230us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.500s	335.230us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.660s	155.096us	1	1	100.00
		i2c_csr_rw	1.660s	70.050us	1	1	100.00
		i2c_csr_aliasing	2.420s	94.500us	1	1	100.00
		i2c_same_csr_outstanding	1.610s	34.205us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.660s	155.096us	1	1	100.00
		i2c_csr_rw	1.660s	70.050us	1	1	100.00
		i2c_csr_aliasing	2.420s	94.500us	1	1	100.00
		i2c_same_csr_outstanding	1.610s	34.205us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.020s	74.494us	1	1	100.00
		i2c_sec_cm	1.620s	286.161us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.020s	74.494us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	16.200s	884.136us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.880s	499.337us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	6.110s	443.914us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.18650709931474461234986904206857363547685490326155656328664188310166062712415
    Line 85, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 884136237 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 884136237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.42597430030493797715854761783429875211031383197867420771577185366082851547458
    Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 443914058 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 443914058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.47166462289241335466214898051132286495745650991223228263612396109161995816219
Line 214, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 62503009113 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2954444

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.52281058485604595052303563773102281633513840596548364515356299649426098630539
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 499336977 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 499336977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.59985726064301572358503988391699781227589220372386647703637644555938920047929
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10050619549 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10050619549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```