KEYMGR Simulation Results

Tuesday May 27 2025 17:01:21 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	18.230s	2.911ms	1	1	100.00
V1	random	keymgr_random	6.910s	804.613us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.890s	124.496us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.560s	11.408us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	2.040s	129.908us	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	7.450s	373.663us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.910s	47.581us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.560s	11.408us	1	1	100.00
		keymgr_csr_aliasing	7.450s	373.663us	0	1	0.00
V1		TOTAL			5	7	71.43
V2	cfgen_during_op	keymgr_cfg_regwen	2.190s	18.080us	1	1	100.00
V2	sideload	keymgr_sideload	2.300s	71.230us	1	1	100.00
		keymgr_sideload_kmac	3.630s	164.190us	1	1	100.00
		keymgr_sideload_aes	2.860s	55.617us	1	1	100.00
		keymgr_sideload_otbn	2.710s	46.300us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	3.070s	62.952us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.000s	89.266us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.760s	157.902us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.320s	92.919us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	4.180s	83.788us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	3.140s	68.423us	1	1	100.00
V2	stress_all	keymgr_stress_all	10.710s	374.852us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.590s	12.253us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.600s	86.139us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.070s	517.763us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.070s	517.763us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.890s	124.496us	1	1	100.00
		keymgr_csr_rw	1.560s	11.408us	1	1	100.00
		keymgr_csr_aliasing	7.450s	373.663us	0	1	0.00
		keymgr_same_csr_outstanding	2.530s	146.760us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.890s	124.496us	1	1	100.00
		keymgr_csr_rw	1.560s	11.408us	1	1	100.00
		keymgr_csr_aliasing	7.450s	373.663us	0	1	0.00
		keymgr_same_csr_outstanding	2.530s	146.760us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	5.580s	1.196ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	5.580s	1.196ms	1	1	100.00
		keymgr_tl_intg_err	2.370s	138.459us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.680s	254.560us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.680s	254.560us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.680s	254.560us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.680s	254.560us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	6.980s	407.588us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	5.580s	1.196ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	5.580s	1.196ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	2.370s	138.459us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.680s	254.560us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.190s	18.080us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	6.910s	804.613us	1	1	100.00
		keymgr_csr_rw	1.560s	11.408us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	6.910s	804.613us	1	1	100.00
		keymgr_csr_rw	1.560s	11.408us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	6.910s	804.613us	1	1	100.00
		keymgr_csr_rw	1.560s	11.408us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.000s	89.266us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	4.180s	83.788us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	4.180s	83.788us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	6.910s	804.613us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	9.770s	1.411ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	5.580s	1.196ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	5.580s	1.196ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	5.580s	1.196ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.040s	62.850us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.000s	89.266us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	5.580s	1.196ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	5.580s	1.196ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	5.580s	1.196ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.040s	62.850us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.040s	62.850us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	5.580s	1.196ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.040s	62.850us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	5.580s	1.196ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.040s	62.850us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	3.710s	256.680us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			26	30	86.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 3 failures:

  • Test keymgr_tl_intg_err has 1 failures.

    • 0.keymgr_tl_intg_err.55253435535425798767197755799620695606420397230395986486724651759162536676530
      Line 107, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
        UVM_ERROR @ 138459146 ps: (keymgr_csr_assert_fpv.sv:459) [ASSERT FAILED] attest_sw_binding_5_rd_A
        UVM_INFO @ 138459146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_bit_bash has 1 failures.

    • 0.keymgr_csr_bit_bash.609291027844974096103846437873940364444117051312633838940215906729832527858
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
        UVM_ERROR @ 129907766 ps: (keymgr_csr_assert_fpv.sv:449) [ASSERT FAILED] attest_sw_binding_3_rd_A
        UVM_INFO @ 129907766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_aliasing has 1 failures.

    • 0.keymgr_csr_aliasing.75212633252823901897050076124594480642858046363700472782654902941421790955153
      Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[6] & 'hffffffff)))'
        UVM_ERROR @ 373662710 ps: (keymgr_csr_assert_fpv.sv:399) [ASSERT FAILED] sealing_sw_binding_1_rd_A
        UVM_INFO @ 373662710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.105321867684698291619150231769508615418581060564127562830111704429937950869224
      Line 379, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 256680306 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 256680306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---