KMAC/MASKED Simulation Results

Tuesday May 27 2025 17:01:21 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	58.920s	19.642ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.820s	71.597us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.900s	60.195us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.190s	513.980us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.020s	294.068us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.770s	452.557us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.900s	60.195us	1	1	100.00
		kmac_csr_aliasing	4.020s	294.068us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.740s	19.567us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.050s	72.185us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	7.923m	26.440ms	1	1	100.00
V2	burst_write	kmac_burst_write	7.424m	21.812ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.530s	9.347ms	1	1	100.00
		kmac_test_vectors_sha3_256	30.720s	32.879ms	1	1	100.00
		kmac_test_vectors_sha3_384	24.896m	68.983ms	1	1	100.00
		kmac_test_vectors_sha3_512	17.481m	32.650ms	1	1	100.00
		kmac_test_vectors_shake_128	2.800m	12.131ms	1	1	100.00
		kmac_test_vectors_shake_256	22.814m	16.637ms	1	1	100.00
		kmac_test_vectors_kmac	3.190s	89.153us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.820s	152.880us	1	1	100.00
V2	sideload	kmac_sideload	3.322m	3.519ms	1	1	100.00
V2	app	kmac_app	1.775m	5.004ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.000s	464.394us	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.329m	4.441ms	1	1	100.00
V2	error	kmac_error	1.567m	7.243ms	1	1	100.00
V2	key_error	kmac_key_error	2.230s	84.535us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.510s	165.917us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	16.090s	625.070us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	34.180s	2.407ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	47.420s	18.276ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	6.660s	871.952us	1	1	100.00
V2	stress_all	kmac_stress_all	6.270s	152.095us	1	1	100.00
V2	intr_test	kmac_intr_test	1.610s	14.095us	1	1	100.00
V2	alert_test	kmac_alert_test	1.930s	55.228us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.320s	108.164us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.320s	108.164us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.820s	71.597us	1	1	100.00
		kmac_csr_rw	1.900s	60.195us	1	1	100.00
		kmac_csr_aliasing	4.020s	294.068us	1	1	100.00
		kmac_same_csr_outstanding	3.090s	338.766us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.820s	71.597us	1	1	100.00
		kmac_csr_rw	1.900s	60.195us	1	1	100.00
		kmac_csr_aliasing	4.020s	294.068us	1	1	100.00
		kmac_same_csr_outstanding	3.090s	338.766us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.470s	310.462us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.470s	310.462us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.470s	310.462us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.470s	310.462us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.810s	23.421us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	37.430s	3.647ms	1	1	100.00
		kmac_tl_intg_err	4.510s	374.170us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.510s	374.170us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	6.660s	871.952us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	58.920s	19.642ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.322m	3.519ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.470s	310.462us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	37.430s	3.647ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	37.430s	3.647ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	37.430s	3.647ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	58.920s	19.642ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	6.660s	871.952us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	37.430s	3.647ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.135m	49.070ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	58.920s	19.642ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	36.120s	3.622ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.73650425487452140586917736448311080707521892068729034582280801810926265101258
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
        UVM_ERROR @  23421110 ps: (kmac_csr_assert_fpv.sv:515) [ASSERT FAILED] prefix_4_rd_A
        UVM_INFO @  23421110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---